公开(公告)号：US09318183B2

公开(公告)日：2016-04-19

申请号：US14937788

申请日：2015-11-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

IPC: G06F13/00 ,  G11C11/406 ,  G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1636 ,  G06F13/1689 ,  G06Q10/00 ,  G06Q20/00 ,  G11C7/02 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4061

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

公开(公告)号：US09304530B1

公开(公告)日：2016-04-05

申请号：US13946864

申请日：2013-07-19

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F1/04 ,  G06F1/08 ,  G11C7/22

CPC classification number: G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222

Abstract: A strobed signaling interface generates a reduced-frequency replica of an incoming strobe signal and applies the replica to extend the interval over which strobe-sampled write data values remain available for transfer to a clocked timing domain. Quadrature instances of the reduced-frequency strobe replicas may be generated and occasionally sampled by skew control logic within the memory component to obtain a coarse measure of the skew between the strobed and clocked timing domains. When the strobe-to-clock domain skew is outside a predetermined boundary, the skew control logic selects an alternative clock signal edge (i.e., earlier or later edge) to sample strobed data, thereby reducing the effective skew between the two timing domains.

Abstract translation: 选通信令接口产生输入选通信号的降频复本，并应用副本以延长选通脉冲采样的写入数据值可用于传输到时钟定时域的间隔。 缩小频率选通副本的正交实例可以由存储器组件内的偏斜控制逻辑产生并偶尔采样，以获得选通和时钟定时域之间的偏斜的粗略度量。 当选通时钟域偏移超出预定边界时，偏斜控制逻辑选择替代时钟信号边沿（即较早或更晚的边缘）对选通数据进行采样，从而减少两个定时域之间的有效偏移。

公开(公告)号：US20160064066A1

公开(公告)日：2016-03-03

申请号：US14937788

申请日：2015-11-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John E. Poulton

IPC: G11C11/406 ,  G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1636 ,  G06F13/1689 ,  G06Q10/00 ,  G06Q20/00 ,  G11C7/02 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4061

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

Abstract translation: 一种系统包括存储器控制器和具有命令接口和多个存储器组的存储器件，每个存储体具有多行存储器单元。 存储器控制器向存储器件发送自动刷新命令。 响应于自动刷新命令，在第一时间间隔期间，存储器件执行刷新操作以刷新存储器单元，并且存储器件的命令接口在第一时间间隔的持续时间内被置于校准模式。 同时，在第一时间间隔的至少一部分期间，存储器控制器执行存储器件的命令接口的校准。 自动刷新命令可以指定要刷新存储器件的存储体的顺序，使得存储器件以指定的存储体顺序顺序地刷新多个存储体中的相应行。

公开(公告)号：US09274892B2

公开(公告)日：2016-03-01

申请号：US14828013

申请日：2015-08-17

Applicant: Rambus Inc.

Inventor： Ely K. Tsern ,  Mark A. Horowitz ,  Frederick A. Ware

IPC: G06F11/00 ,  G06F3/06 ,  G11C29/52 ,  G06F11/14 ,  G06F11/10 ,  G06F11/07 ,  H04L1/00 ,  H04L1/08 ,  H04L1/18

CPC classification number: G06F11/073 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/006 ,  G06F11/0745 ,  G06F11/0766 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/1402 ,  G06F11/141 ,  G06F11/1443 ,  G06F11/20 ,  G11C29/52 ,  H03M13/03 ,  H04L1/0057 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1809

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Abstract translation: 存储器系统包括具有至少一个信号线的链路和控制器。 所述控制器包括耦合到所述链路以发送第一数据的至少一个发射机，以及耦合到所述发射机的第一误差保护发生器。 第一错误保护发生器动态地将错误检测码添加到第一数据的至少一部分。 至少一个接收器耦合到链路以接收第二数据。 第一错误检测逻辑确定控制器接收到的第二数据是否包含至少一个错误，并且如果检测到错误则断言第一错误状况。 该系统包括具有耦合到链路以传输第二数据的至少一个存储器件发送器的存储器件。 耦合到存储器件发射器的第二误差保护发生器动态地将错误检测码添加到第二数据的至少一部分。

公开(公告)号：US09262342B2

公开(公告)日：2016-02-16

申请号：US14133383

申请日：2013-12-18

Applicant: RAMBUS INC.

Inventor： Trung Am Diep ,  Pradeep Batra ,  Brian S. Leibowitz ,  Frederick A. Ware

IPC: G06F12/00 ,  G06F12/14 ,  G06F21/79 ,  G06F12/10

CPC classification number: G06F21/79 ,  G06F12/1009 ,  G06F12/1408 ,  G06F2212/1052 ,  G06F2221/2107 ,  H04L9/30

Abstract: A memory controller encrypts contents of a page frame based at least in part on a frame key associated with the page frame. The memory controller generates a first encrypted version of the frame key based at least in part on a first process key associated with a first process, wherein the first encrypted version of the frame key is stored in a first memory table associated with the first process. The memory controller generates a second encrypted version of the frame key based at least in part on a second process key associated with a second process, wherein the second encrypted version of the frame key is stored in a second memory table associated with the second process, the first process and the second process sharing access to the page frame using the first encrypted version of the frame key and the second encrypted version of the frame key, respectively.

Abstract translation: 存储器控制器至少部分地基于与页面帧相关联的帧密钥来加密页面帧的内容。 所述存储器控制器至少部分地基于与第一进程相关联的第一进程密钥来生成所述帧密钥的第一加密版本，其中所述帧密钥的所述第一加密版本被存储在与所述第一进程相关联的第一存储器表中。 所述存储器控制器至少部分地基于与第二进程相关联的第二进程密钥来生成所述帧密钥的第二加密版本，其中所述帧密钥的所述第二加密版本被存储在与所述第二进程相关联的第二存储器表中， 第一进程和第二进程分别使用帧密钥的第一加密版本和帧密钥的第二加密版本共享对页面帧的访问。

公开(公告)号：US09256557B2

公开(公告)日：2016-02-09

申请号：US14558517

申请日：2014-12-02

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware

IPC: G06F13/16 ,  G06F13/42 ,  G11C7/10 ,  G11C5/04 ,  H05K1/18

CPC classification number: G06F13/1642 ,  G06F12/1081 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/28 ,  G06F13/4243 ,  G06F2212/656 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1075 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/10159 ,  Y02D10/14 ,  Y02D10/151 ,  Y02P70/611

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Abstract translation: 具有减小的访问粒度的存储器模块。 存储器模块包括其上具有信号线的衬底，其形成控制路径和第一和第二数据路径，并且还包括共同耦合到控制路径并分别耦合到第一和第二数据路径的第一和第二存储器件。 第一和第二存储器件包括控制电路，用于响应于第一和第二存储器访问命令，经由控制路径接收相应的第一和第二存储器访问命令并且执行第一和第二数据路径上的并发数据传输。

公开(公告)号：US09232651B2

公开(公告)日：2016-01-05

申请号：US14687687

申请日：2015-04-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan

IPC: H05K1/11 ,  G11C11/4093 ,  H05K1/18 ,  G06F15/78 ,  G11C11/408 ,  G06F13/16 ,  G06F13/40 ,  G06F1/18 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  H01R3/00 ,  H03M9/00

CPC classification number: H05K1/11 ,  G06F1/184 ,  G06F13/1694 ,  G06F13/4068 ,  G06F15/7803 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4082 ,  G11C11/4093 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a motherboard substrate includes first and second sets of data lines, the first set of data lines arranged into a first set of nibbles and the second set of data lines are arranged into a second set of nibbles with each of the first and the second sets of nibbles including a respective timing line for a respective timing signal. The motherboard substrate also includes a processor socket connected to the first set of data lines, a first slot connected to the processor socket via a first subset of the first set of nibbles, and a second slot connected to the processor socket via a second subset of the first set of nibbles and connected to the first slot via the second set of nibbles.

Abstract translation: 这里描述的实施例描述了用于存储器系统的技术。 主板基板的一个实现包括第一和第二组数据线，布置成第一组半字节的第一组数据线和第二组数据线被布置成第二组半字节，其中第一和第 第二组半字节包括用于相应定时信号的相应定时线。 主板基板还包括连接到第一组数据线的处理器插座，经由第一组半字节的第一子集连接到处理器插座的第一插槽，以及经由第二组子集 第一组半字节，并通过第二组半字节连接到第一个插槽。

公开(公告)号：US20150378817A1

公开(公告)日：2015-12-31

申请号：US14827978

申请日：2015-08-17

Applicant: Rambus Inc.

Inventor： Ely K. Tsern ,  Mark A. Horowitz ,  Frederick A. Ware

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/073 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/006 ,  G06F11/0745 ,  G06F11/0766 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/1402 ,  G06F11/141 ,  G06F11/1443 ,  G06F11/20 ,  G11C29/52 ,  H03M13/03 ,  H04L1/0057 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1809

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Abstract translation: 存储器系统包括具有至少一个信号线的链路和控制器。 所述控制器包括耦合到所述链路以发送第一数据的至少一个发射机，以及耦合到所述发射机的第一误差保护发生器。 第一错误保护发生器动态地将错误检测码添加到第一数据的至少一部分。 至少一个接收器耦合到链路以接收第二数据。 第一错误检测逻辑确定控制器接收到的第二数据是否包含至少一个错误，并且如果检测到错误则断言第一错误状况。 该系统包括具有耦合到链路以传输第二数据的至少一个存储器件发送器的存储器件。 耦合到存储器件发射器的第二误差保护发生器动态地将错误检测码添加到第二数据的至少一部分。

公开(公告)号：US09219509B1

公开(公告)日：2015-12-22

申请号：US13963321

申请日：2013-08-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: H04L25/00 ,  H04B1/10 ,  H04B1/04 ,  H04L12/70 ,  G06F13/42 ,  H04L12/935 ,  G06F7/76 ,  G06F12/06

CPC classification number: H04B1/10 ,  G06F7/76 ,  G06F12/0607 ,  G06F13/4013 ,  G06F13/4204 ,  G09G2360/123 ,  H04L49/3018 ,  H04L2012/5679 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system and method for reordering transmitted bits to minimize the number of bit transitions per bit time, reducing system power consumption and signaling noise. Bit reordering is accomplished by performing skip operations, where to-be-transmitted bits are replaced by one or more bits in the bit stream at given bit times. DBI may be used in addition, or as an alternative, to bit reordering to further minimize the number of bit transitions per bit time. A receiver performs operations necessary to restore bits to their original sequence and/or recover the bits in their non-inverted form.

Abstract translation: 一种用于重新排序发送位的系统和方法，以最小化每位时间的位转换次数，减少系统功耗和信号噪声。 通过执行跳过操作来完成比特重排序，在给定的比特时间，将被发送的比特由比特流中的一个或多个比特替换。 或者作为替代，可以将DBI用作位重排序以进一步最小化每位时间的位转换的数量。 接收机执行将比特恢复到其原始序列所需的操作和/或以非反相形式恢复比特。

公开(公告)号：US20150349798A1

公开(公告)日：2015-12-03

申请号：US14823826

申请日：2015-08-11

Applicant: Rambus Inc.

Inventor： Yuanlong Wang ,  Frederick A. Ware

IPC: H03M13/09 ,  H03M13/00 ,  G06F11/10

CPC classification number: G06F11/0727 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1402 ,  G06F13/4286 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/611 ,  H04L1/0003 ,  H04L1/0008 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1867 ,  H04L2001/0093

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract translation: 控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。 编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。 耦合到链路接口的发射机是发送写入数据。 延迟元件耦合到编码器的输出。 耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。 错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。 错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。