公开(公告)号：US07381451B1

公开(公告)日：2008-06-03

申请号：US10991890

申请日：2004-11-17

Applicant: Chi-i Lang ,  Ratsamee Limdulpaiboon ,  Cayetano Gonzalez

Inventor： Chi-i Lang ,  Ratsamee Limdulpaiboon ,  Cayetano Gonzalez

IPC: H05H1/24 ,  B05D3/02 ,  H05H1/02

CPC classification number: C23C16/402 ,  C23C16/56 ,  H01J37/3244 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7846

Abstract: High density plasma (HDP) techniques form high tensile stress silicon oxide films. The HDP techniques use low enough temperatures to deposit high tensile stress silicon oxide films in transistor architectures and fabrication processes effective for generating channel strain without adversely impacting transistor integrity. Methods involve a two phase process: a HDP deposition phase, wherein silanol groups are formed in the silicon oxide film, and a bond reconstruction phase, wherein water is removed and tensile stress is induced in the silicon oxide film. Transistor strain can be generated in NMOS or PMOS devices using strategic placement of the high tensile stress silicon oxide. Example applications include high tensile stress silicon oxides for use in shallow trench isolation structures, pre-metal dielectric layer and silicon on insulator substrates.

Abstract translation: 高密度等离子体（HDP）技术形成高拉伸应力氧化硅膜。 HDP技术使用足够低的温度在晶体管架构和制造工艺中沉积高拉伸应力氧化硅膜，这有效地用于产生通道应变而不会不利地影响晶体管的完整性。 方法涉及两相工艺：HDP沉积相，其中在氧化硅膜中形成硅烷醇基团，以及键合重构阶段，其中除去水并在氧化硅膜中引发拉伸应力。 晶体管应变可以在NMOS或PMOS器件中使用高拉伸应力氧化硅的策略放置来产生。 示例性应用包括用于浅沟槽隔离结构，预金属介电层和绝缘体上硅衬底的高拉伸应力氧化硅。

公开(公告)号：US20070166989A1

公开(公告)日：2007-07-19

申请号：US11647882

申请日：2006-12-29

Applicant: Zachary Fresco ,  Chi-I Lang ,  Sandra Malhotra ,  Tony Chiang ,  Thomas Boussie ,  Nitin Kumar ,  Jinhong Tong ,  Anh Duong

Inventor： Zachary Fresco ,  Chi-I Lang ,  Sandra Malhotra ,  Tony Chiang ,  Thomas Boussie ,  Nitin Kumar ,  Jinhong Tong ,  Anh Duong

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/31

CPC classification number: H01L21/288 ,  B82Y30/00 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685

Abstract: Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.

Abstract translation: 描述基板处理方法。 所述方法包括在基底上形成材料层。 所述方法包括选择分子屏蔽层（MML）的成分以消除作为衬底处理的结果的材料层中的变化的影响。 所述方法包括通过在材料层上选择性地沉积MML来使材料层的表面特性归一化。

公开(公告)号：US07157384B2

公开(公告)日：2007-01-02

申请号：US11021319

申请日：2004-12-22

Applicant: Kang Sub Yim ,  Melissa M. Tam ,  Dian Sugiarto ,  Chi-I Lang ,  Peter Wai-Man Lee ,  Li-Qun Xia

Inventor： Kang Sub Yim ,  Melissa M. Tam ,  Dian Sugiarto ,  Chi-I Lang ,  Peter Wai-Man Lee ,  Li-Qun Xia

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/76834 ,  C23C16/30 ,  C23C16/325 ,  C23C16/401 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/3127 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832

Abstract: Methods are provided for depositing a silicon carbide layer having significantly reduced current leakage. The silicon carbide layer may be a barrier layer or part of a barrier bilayer that also includes a barrier layer. Methods for depositing oxygen-doped silicon carbide barrier layers are also provided. The silicon carbide layer may be deposited by reacting a gas mixture comprising an organosilicon compound, an aliphatic hydrocarbon comprising a carbon-carbon double bond or a carbon-carbon triple bond, and optionally, helium in a plasma. Alternatively, the silicon carbide layer may be deposited by reacting a gas mixture comprising hydrogen or argon and an organosilicon compound in a plasma.

Abstract translation: 提供了用于沉积具有显着降低的电流泄漏的碳化硅层的方法。 碳化硅层可以是还包括阻挡层的阻挡层或阻挡层双层的一部分。 还提供了沉积氧掺杂的碳化硅阻挡层的方法。 可以通过使包含有机硅化合物，包含碳 - 碳双键或碳 - 碳三键的脂族烃和任选地在等离子体中的氦气的气体混合物反应来沉积碳化硅层。 或者，可以通过在等离子体中使包含氢或氩的气体混合物和有机硅化合物反应来沉积碳化硅层。

公开(公告)号：US06849562B2

公开(公告)日：2005-02-01

申请号：US10092203

申请日：2002-03-04

Applicant: Chi-I Lang ,  Li-Qun Xia ,  Ping Xu ,  Louis Yang

Inventor： Chi-I Lang ,  Li-Qun Xia ,  Ping Xu ,  Louis Yang

IPC: C23C16/36 ,  H01L21/31 ,  H01L21/469

CPC classification number: C23C16/36

Abstract: A method for depositing a low k dielectric film comprising silicon, carbon, and nitrogen is provided. The low k dielectric film is formed by a gas mixture comprising a silicon source, a carbon source, and NR1R2R3, wherein R1, R2, and R3 are selected from the group consisting of alkyl and phenyl groups. The low k dielectric film may be used as a barrier layer, an etch stop, an anti-reflective coating, or a hard mask.

Abstract translation: 提供了沉积包含硅，碳和氮的低k电介质膜的方法。 低k电介质膜由包含硅源，碳源和NR1R2R3的气体混合物形成，其中R1，R2和R3选自烷基和苯基。 低k电介质膜可以用作阻挡层，蚀刻停止层，抗反射涂层或硬掩模。

公开(公告)号：US08859427B2

公开(公告)日：2014-10-14

申请号：US13335011

申请日：2011-12-22

Applicant: Bob Kong ,  Tony Chiang ,  Chi-I Lang ,  Zhi-Wen Sun ,  Jinhong Tong

Inventor： Bob Kong ,  Tony Chiang ,  Chi-I Lang ,  Zhi-Wen Sun ,  Jinhong Tong

IPC: H01L21/302 ,  C23C18/54 ,  H01L21/288 ,  H01L21/768 ,  H01L21/02 ,  C23C18/16

CPC classification number: H01L21/02068 ,  C23C18/1651 ,  C23C18/54 ,  H01L21/288 ,  H01L21/76852 ,  H01L21/76874

Abstract: Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl3, and a pH adjuster.

Abstract translation: 本发明的实施方案描述了处理半导体衬底的方法，其包括将锌化溶液施加到半导体衬底上以在含钛层上形成锌钝化层，所述锌化溶液包含锌盐FeCl 3和pH调节剂。

公开(公告)号：US08476107B2

公开(公告)日：2013-07-02

申请号：US13096719

申请日：2011-04-28

Applicant: Nitin Kumar ,  Chi-I Lang ,  Tony Chiang ,  Zhi-Wen Sun ,  Jinhong Tong

Inventor： Nitin Kumar ,  Chi-I Lang ,  Tony Chiang ,  Zhi-Wen Sun ,  Jinhong Tong

IPC: H01L21/00

CPC classification number: H01L45/145 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

公开(公告)号：US20130130464A1

公开(公告)日：2013-05-23

申请号：US13302777

申请日：2011-11-22

Applicant: Albert Lee ,  Chi-I Lang

Inventor： Albert Lee ,  Chi-I Lang

IPC: H01L45/00

CPC classification number: H01L45/1616 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/146

Abstract: In some embodiments, the present invention discloses plasma processing at interfaces of an ALD metal oxide film with top and bottom electrodes to improve the ReRAM device characteristics. The interface processing can comprise an oxygen inhibitor step with a bottom polysilicon electrode to prevent oxidation of the polysilicon layer, enhancing the electrical contact of the metal oxide film with the polysilicon electrode. The interface processing can comprise an oxygen enrichment step with a top metal electrode to increase the resistivity of the metal oxide layer, providing an integrated current limiter layer.

Abstract translation: 在一些实施例中，本发明公开了在ALD金属氧化物膜与顶部和底部电极的界面处的等离子体处理，以改善ReRAM器件的特性。 界面处理可以包括具有底部多晶硅电极的氧抑制剂步骤，以防止多晶硅层氧化，增强金属氧化物膜与多晶硅电极的电接触。 界面处理可以包括具有顶部金属电极的富氧步骤以增加金属氧化物层的电阻率，从而提供集成的限流器层。

公开(公告)号：US20120295436A1

公开(公告)日：2012-11-22

申请号：US13547856

申请日：2012-07-12

Applicant: Bob Kong ,  Zhi-Wen Sun ,  Chi-I Lang ,  Jinhong Tong ,  Tony Chiang

Inventor： Bob Kong ,  Zhi-Wen Sun ,  Chi-I Lang ,  Jinhong Tong ,  Tony Chiang

IPC: H01L21/768

CPC classification number: H01L21/02068 ,  C23C18/1651 ,  C23C18/54 ,  H01L21/288 ,  H01L21/76852 ,  H01L21/76874

Abstract: Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl3, and a pH adjuster.

Abstract translation: 本发明的实施方案描述了处理半导体衬底的方法，其包括将锌化溶液施加到半导体衬底上以在含钛层上形成锌钝化层，所述锌化溶液包含锌盐FeCl 3和pH调节剂。

公开(公告)号：US08298891B1

公开(公告)日：2012-10-30

申请号：US12603510

申请日：2009-10-21

Applicant: Tony Chiang ,  Prashant Phatak ,  Chi-I Lang

Inventor： Tony Chiang ,  Prashant Phatak ,  Chi-I Lang

IPC: H01L21/336

CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/148 ,  H01L45/149 ,  H01L45/1616 ,  H01L45/1641

Abstract: A resistive-switching memory element is described. The memory element includes a first electrode, a porous layer over the first electrode including a point defect embedded in a plurality of pores of the porous layer, and a second electrode over the porous layer, wherein the nonvolatile memory element is configured to switch between a high resistive state and a low resistive state.

Abstract translation: 描述电阻式切换存储元件。 所述存储元件包括第一电极，所述第一电极上的多孔层，包括嵌入所述多孔层的多个孔中的点缺陷，以及位于所述多孔层上的第二电极，其中所述非易失性存储元件构造成在 高电阻状态和低电阻状态。

公开(公告)号：US08298837B2

公开(公告)日：2012-10-30

申请号：US13072083

申请日：2011-03-25

Applicant: Yun Wang ,  Tony P. Chiang ,  Chi-I Lang

Inventor： Yun Wang ,  Tony P. Chiang ,  Chi-I Lang

IPC: H01L21/00

CPC classification number: H01L51/0031 ,  H01L51/56

Abstract: A system and method of increasing productivity of OLED material screening includes providing a substrate that includes an organic semiconductor, processing regions on the substrate by combinatorially varying parameters associated with the OLED device production on the substrate, performing a first characterization test on the processed regions on the substrate to generate first results, processing regions on the substrate in a combinatorial manner by varying parameters associated with the OLED device production on the substrate based on the first results of the first characterization test, performing a second characterization test on the processed regions on the substrate to generate second results, and determining whether the substrate meets a predetermined quality threshold based on the second results.

Abstract translation: 提高OLED材料筛选的生产率的系统和方法包括提供包括有机半导体的衬底，通过组合地改变与衬底上的OLED器件生产相关的参数来在衬底上处理区域，对处理的区域进行第一表征测试 所述衬底产生第一结果，基于所述第一表征测试的第一结果，通过改变与所述衬底上的OLED器件生产相关联的参数，以组合方式处理所述衬底上的区域，对所述衬底上的所述处理区域进行第二特性测试 衬底以产生第二结果，以及基于第二结果确定衬底是否满足预定质量阈值。