公开(公告)号：US20080067584A1

公开(公告)日：2008-03-20

申请号：US11522669

申请日：2006-09-17

Applicant: Sik K Lui ,  Francois Hebert ,  Anup Bhalla

Inventor： Sik K Lui ,  Francois Hebert ,  Anup Bhalla

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/781 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.

Abstract translation: 本发明公开了底源横向扩散MOS（BS-LDMOS）器件。 器件具有在半导体衬底的顶表面附近的漏区附近设置的源极区域，该半导体衬底在源极区域和漏极区域之间支撑栅极。 BS-LDMOS器件还具有一个组合的沉陷通道区域，该半导体衬底的深度完全位于靠近顶表面的源极区域附近设置的体区域之下，其中组合沉降通道区域用作掩埋源体 用于将主体区域和源区域电连接到用作源电极的衬底的底部。 漂移区域设置在栅极下方的顶表面附近并且远离源极区域并且延伸到并包围漏极区域。 在漂移区域下方延伸的组合沉降通道区域和具有与掺杂剂 - 导电性相反并补偿漂移区域以减少源极 - 漏极电容的组合沉降沟道区域。

公开(公告)号：US07342433B2

公开(公告)日：2008-03-11

申请号：US11270062

申请日：2005-11-08

Applicant: Richard A. Harris ,  Francois Hebert

Inventor： Richard A. Harris ,  Francois Hebert

IPC: H03K17/687

CPC classification number: H01L27/0266 ,  H02H5/042 ,  H02H5/044 ,  H02H9/025 ,  H02H9/046

Abstract: An apparatus and method for enhanced transient blocking employing a transient blocking unit (TBU) that uses at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device. The interconnection is performed such that a transient alters a bias voltage Vp of the p-channel device and a bias voltage Vn of the n-channel device such that the p- and n-channel devices mutually switch off to block the transient. The apparatus has an enhancer circuit for applying an enhancement bias to a gate terminal of at least one of the depletion mode n-channel devices of the TBU to reduce a total resistance Rtot of the apparatus. Alternatively, the apparatus has an enhancement mode NMOS transistor and a TBU connected thereto to help provide an enhancement bias to a gate terminal of the enhancement mode NMOS.

Abstract translation: 一种用于增强瞬态阻塞的装置和方法，其采用使用与至少一个耗尽型p沟道器件互连的至少一个耗尽型n沟道器件的瞬态阻塞单元（TBU）。 执行互连，使得瞬态改变p沟道器件的偏置电压V P和N沟道器件的偏置电压V N n N，使得p - 和n通道设备相互关闭以阻止瞬态。 该装置具有增强器电路，用于向TBU中的至少一个耗尽型n沟道器件的栅极端子施加增强偏置，以减小器件的总电阻R tht。 或者，该装置具有增强型NMOS晶体管和与其连接的TBU，以帮助向增强型NMOS的栅极端提供增强偏置。

公开(公告)号：US20080023785A1

公开(公告)日：2008-01-31

申请号：US11495803

申请日：2006-07-28

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L23/58 ,  H01L21/336

CPC classification number: H01L29/4175 ,  H01L21/26513 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

Abstract: This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.

Abstract translation: 本发明公开了底源横向扩散MOS（BS-LDMOS）器件。 器件具有在半导体衬底的顶表面附近的漏区附近设置的源极区域，该半导体衬底在源极区域和漏极区域之间支撑栅极。 BS-LDMOS器件还具有一个组合的沉陷通道区域，该半导体衬底的深度完全位于靠近顶表面的源极区域附近设置的体区域之下，其中组合沉降通道区域用作掩埋源体 用于将主体区域和源区域电连接到用作源电极的衬底的底部。 漂移区域设置在栅极下方的顶表面附近并且远离源极区域并且延伸到并包围漏极区域。 在漂移区域下方延伸的组合沉降通道区域和具有与掺杂剂 - 导电性相反并补偿漂移区域以减少源极 - 漏极电容的组合沉降沟道区域。

公开(公告)号：US20080006951A1

公开(公告)日：2008-01-10

申请号：US11444977

申请日：2006-05-31

Applicant: Francois Hebert ,  Anup Bhalla

Inventor： Francois Hebert ,  Anup Bhalla

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/85201 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.

Abstract translation: 公开了一种铜键合兼容的键合焊盘结构及其相关方法。 器件接合焊盘结构包括由互连金属的区域和非导电钝化材料的区域形成的缓冲结构，该缓冲结构为器件的下层和结构提供缓冲。

公开(公告)号：US20070012983A1

公开(公告)日：2007-01-18

申请号：US11487142

申请日：2006-07-14

Applicant: Robert Yang ,  Richard Blanchard ,  Francois Hebert

Inventor： Robert Yang ,  Richard Blanchard ,  Francois Hebert

IPC: H01L29/94

CPC classification number: H01L29/7803 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: This invention relates to achieving high breakdown voltage and low on-resistance in semiconductor devices that have top, intermediate and bottom regions with a controllable current path traversing any of these regions. The device has an insulating trench that is coextensive with the top and intermediate regions and girds these regions from at least one side and preferably from both or all sides. A series capacitive structure with a biased top element and a number of floating elements is disposed in the insulating trench, and the intermediate region is endowed with a capacitive property that is chosen to establish a capacitive interaction or coupling between the series capacitive structure and the intermediate region so that the breakdown voltage VBD is maximized and on-resistance is minimized. A second series capacitive structure disposed in a second insulating trench can be employed to terminate the device.

Abstract translation: 本发明涉及在半导体器件中实现高击穿电压和低导通电阻，所述半导体器件具有穿过任何这些区域的可控电流路径的顶部区域，中间区域和底部区域。 该装置具有与顶部和中间区域共同延伸的绝缘沟槽，并且从至少一个侧面，优选地从两侧或全部侧面将这些区域线化。 具有偏置顶部元件和多个浮动元件的串联电容结构设置在绝缘沟槽中，并且中间区域具有被选择用于建立串联电容结构和中间体之间的电容性相互作用或耦合的电容性质 区域，使得击穿电压V BAT最大化，导通电阻最小化。 可以采用设置在第二绝缘沟槽中的第二串联电容结构来终止该器件。

公开(公告)号：US20060238936A1

公开(公告)日：2006-10-26

申请号：US11410575

申请日：2006-04-24

Applicant: Richard Blanchard ,  Richard Harris ,  Francois Hebert

Inventor： Richard Blanchard ,  Richard Harris ,  Francois Hebert

IPC: H02H9/00

CPC classification number: H01J1/72 ,  C09K11/59 ,  H01H9/548 ,  H02H9/025

Abstract: An apparatus and a method for uni-directional and bi-directional transient blocking. The uni-directional apparatus has a depletion mode n-channel device at its input and a normally closed relay, e.g., a micro-electro-mechanical (MEM) relay, interconnected with the depletion mode n-channel device and the input in such a way that at a predetermined current value the transient causes the normally closed relay to switch into an open state and apply a bias voltage Vn on the depletion mode n-channel device that is sufficiently high to switch it “off” thus block the transient. An analogous arrangement at the output taking advantage of the same or a second relay renders the apparatus bi-directional. The structure of the apparatus and the method of operation ensure a reliable and repeatable trip current Itrip and render the apparatus very robust and feasible for low-cost manufacture.

Abstract translation: 一种用于单向和双向瞬态阻塞的装置和方法。 单向设备在其输入端具有耗尽模式n沟道器件和常闭继电器，例如与耗尽型n沟道器件互连的微机电（MEM）继电器，以及在这种 在预定电流值下，瞬态使常闭继电器切换到打开状态，并在足够高以切换它的耗尽型n沟道器件上施加偏置电压V N“ 关闭“从而阻止瞬态。 利用相同或第二中继器在输出端处的类似布置使设备双向。 该装置的结构和操作方法确保了可靠且可重复的跳闸电流跳闸，并且使得该装置非常坚固且可用于低成本制造。

公开(公告)号：US20060098373A1

公开(公告)日：2006-05-11

申请号：US11130793

申请日：2005-05-17

Applicant: Francois Hebert ,  Richard Harris

Inventor： Francois Hebert ,  Richard Harris

IPC: H02H9/06

CPC classification number: H01L27/0266 ,  H01L21/823462 ,  H01L27/088 ,  H02H9/025 ,  H02H9/046

Abstract: A TBU system that includes a TBU combined with control and monitoring features. For example, in one embodiment, TBU elements are combined with a status indication switch or indicator. In another embodiment, TBU elements are combined with event logging for over voltage conditions, over current conditions, including an indication of when the event occurred and an amount of energy that was let through.

Abstract translation: 一个TBU系统，包括TBU与控制和监控功能相结合。 例如，在一个实施例中，TBU元件与状态指示开关或指示器组合。 在另一个实施例中，TBU元件与过电压条件的事件记录相结合，包括当前状况的发生以及通过的能量的指示。

公开(公告)号：US20060071269A1

公开(公告)日：2006-04-06

申请号：US11282245

申请日：2005-11-18

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L21/26513 ,  H01L21/2658 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1083 ,  H01L29/7833

Abstract: A high voltage MOS transistor is provided that is compatible with low-voltage, sub-micron CMOS and BiCMOS processes. The high voltage transistor of the present invention has dopants that are implanted into the substrate prior to formation of the epitaxial layer. The implanted dopants diffuse into the epitaxial layer from the substrate during the formation of the epitaxial layer and subsequent heating steps. The implanted dopants increase the doping concentration in a lower portion of the epitaxial layer. The implanted dopants may diffuse father into the epitaxial layer than dopants in the buried layer forming an up-retro well that prevents vertical punch-through at high operating voltages for thin epitaxial layers. In addition, the doping concentration below the gate may be light so that the threshold voltage of the transistor is low. Also, the high voltage transistor of the present invention may be isolated from the substrate and the buried layer, and have symmetrical source and drain regions so that it can be used as a pass transistor.

公开(公告)号：US06492678B1

公开(公告)日：2002-12-10

申请号：US09564108

申请日：2000-05-03

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L2976

CPC classification number: H01L29/402 ,  H01L29/42376 ,  H01L29/7835

Abstract: A high voltage MOS transistor with a gate extension that has a reduced electric field in the drain region near the gate is provided. The high voltage MOS transistor includes a first and second gate layers, and a dielectric layer between the gate layers. The first and second gate layers are electrically coupled together and form the gate of the transistor. The second gate layer extends over the drain of the transistor above the dielectric and gate oxide layers to form the gate extension. The high voltage MOS transistor of the present invention may be fabricated without additional processing steps in BiCMOS and CMOS processes that use dual polysilicon layers and a dielectric layer that are used to form capacitors.

Abstract translation: 提供具有在栅极附近的漏极区域中具有减小的电场的栅极延伸的高压MOS晶体管。 高压MOS晶体管包括第一和第二栅极层以及栅极层之间的介电层。 第一和第二栅极层电耦合在一起并形成晶体管的栅极。 第二栅极层在电介质和栅极氧化物层上方的晶体管的漏极上延伸以形成栅极延伸。 本发明的高电压MOS晶体管可以在不使用BiCMOS和CMOS工艺中的附加处理步骤的情况下制造，所述工艺使用双重多晶硅层和用于形成电容器的电介质层。

公开(公告)号：US06215152B1

公开(公告)日：2001-04-10

申请号：US09130192

申请日：1998-08-05

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L2972

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7835

Abstract: A MOSFET has a buried shield plate under the gate and over the drain with the gate being formed on the periphery of the buried shield plate as a self-aligned structure with minimal or no overlap of the gate over the shield plate. Methods of fabricating the MOSFET are disclosed.

Abstract translation: MOSFET在栅极下方和漏极上具有埋置的屏蔽板，栅极作为自对准结构形成在掩埋屏蔽板的周边上，栅极在屏蔽板上的重叠不大或没有重叠。 公开了制造MOSFET的方法。