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106 条记录 (耗时 0.018 秒)

    Resistive RAM having at least one varistor and methods of operating the same
    84.
    发明授权
    Resistive RAM having at least one varistor and methods of operating the same 有权
    具有至少一个压敏电阻的电阻RAM及其操作方法

    公开(公告)号：US07714313B2

    公开(公告)日：2010-05-11

    申请号：US11655086

    申请日：2007-01-19

    申请人： Jung-Hyun Lee ,  Eun-Hong Lee ,  Sang-Jun Choi ,  In-Kyeong Yoo ,  Myoung-Jae Lee

    发明人： Jung-Hyun Lee ,  Eun-Hong Lee ,  Sang-Jun Choi ,  In-Kyeong Yoo ,  Myoung-Jae Lee

    IPC分类号： H01L47/00

    CPC分类号： G11C13/003 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/76

    摘要： Resistive memory devices having at least one varistor and methods of operating the same are disclosed. The resistive memory device may include at least one bottom electrode line, at least one top electrode line crossing the at least one bottom electrode line, and at least one stack structure disposed at an intersection of the at least one top electrode line and the at least one bottom electrode line including a varistor and a data storage layer.

    摘要翻译： 公开了具有至少一个压敏电阻的电阻式存储器件及其操作方法。 电阻式存储器件可以包括至少一个底部电极线，与至少一个底部电极线交叉的至少一个顶部电极线以及至少一个堆叠结构，该至少一个堆叠结构设置在至少一个顶部电极线和至少一个顶部电极线的交点处 一个底部电极线包括变阻器和数据存储层。

    Transistor, method of manufacturing transistor, and method of operating transistor
    86.
    发明申请
    Transistor, method of manufacturing transistor, and method of operating transistor 失效
    晶体管，晶体管的制造方法以及晶体管的工作方法

    公开(公告)号：US20090186444A1

    公开(公告)日：2009-07-23

    申请号：US12216742

    申请日：2008-07-10

    申请人： Choong-Rae Cho ,  In-Kyeong Yoo ,  Myoung-Jae Lee

    发明人： Choong-Rae Cho ,  In-Kyeong Yoo ,  Myoung-Jae Lee

    IPC分类号： H01L21/20

    CPC分类号： H01L29/685

    摘要： A transistor in which a physical property of its channel is changed according to an applied voltage, and methods of manufacturing and operating the same are provided. The transistor may include a first conductive layer on a substrate, a phase change layer and a second conductive layer which are sequentially stacked on the first conductive layer, a first current direction limiting unit and a second current direction limiting unit formed on the second conductive layer by being separated within a space, a third conductive layer and a fourth conductive layer formed on the first current direction limiting unit and the second current direction limiting unit, respectively, a word line connected to the third conductive layer, a bit line connected to the fourth conductive layer, and a voltage lowering unit connected to the word line.

    摘要翻译： 提供其通道的物理特性根据施加的电压而改变的晶体管，并且提供其制造和操作方法。 晶体管可以包括基板上的第一导电层，相继层叠在第一导电层上的相变层和第二导电层，形成在第二导电层上的第一电流方向限制单元和第二电流方向限制单元 通过在空间内分离，分别形成在第一电流方向限制单元和第二电流方向限制单元上的第三导电层和第四导电层，连接到第三导电层的字线，连接到第三导电层的位线 第四导电层和连接到字线的降压单元。