公开(公告)号：US20190067094A1

公开(公告)日：2019-02-28

申请号：US16105802

申请日：2018-08-20

Applicant: ASM IP Holding B.V.

Inventor： Bhushan Zope ,  Kiran Shrestha ,  Shankar Swaminathan ,  Chiyu Zhu ,  Henri Tuomas Antero Jussila ,  Qi Xie

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  C23C16/02 ,  C23C16/14

Abstract: Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process are disclosed. The methods may include: providing a substrate comprising a dielectric surface into a reaction chamber; depositing a nucleation film directly on the dielectric surface; and depositing a molybdenum metal film directly on the nucleation film, wherein depositing the molybdenum metal film includes: contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor; and contacting the substrate with a second vapor phase reactant comprising a reducing agent precursor. Semiconductor device structures including a molybdenum metal film disposed over a surface of a dielectric material with an intermediate nucleation film are also disclosed.

公开(公告)号：US10121699B2

公开(公告)日：2018-11-06

申请号：US15432263

申请日：2017-02-14

Applicant: ASM IP Holding B.V.

Inventor： Han Wang ,  Qi Xie ,  Delphine Longrie ,  Jan Willem Maes ,  David de Roest ,  Julian Hsieh ,  Chiyu Zhu ,  Timo Asikainen ,  Krzysztof Kachel ,  Harald Profijt

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/532 ,  H01L21/283

Abstract: Methods are provided for selectively depositing Al and N containing material on a first conductive surface of a substrate relative to a second, dielectric surface of the same substrate. In some aspects, methods of forming an Al and N containing protective layer or etch stop layer for use in integrated circuit fabrication are provided.

公开(公告)号：US20180190793A1

公开(公告)日：2018-07-05

申请号：US15394571

申请日：2016-12-29

Applicant: ASM IP Holding B.V.

Inventor： Harald Profijt ,  Qi Xie ,  Jan Willem Maes ,  David Kohen

IPC: H01L29/66 ,  H01L29/161 ,  H01L29/10 ,  H01L29/06 ,  H01L21/223

CPC classification number: H01L21/225 ,  H01L21/223 ,  H01L21/2251 ,  H01L21/2256 ,  H01L21/385 ,  H01L21/76858 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/66666

Abstract: In some embodiments, a compound semiconductor is formed by diffusion of semiconductor species from a source semiconductor layer into semiconductor material in a substrate. The source semiconductor layer may be an amorphous or polycrystalline structure, and provides a source of semiconductor species for later diffusion into the other semiconductor material. Advantageously, such a semiconductor layer may be more conformal than an epitaxially grown, crystalline semiconductor layer. As a result, this more conformal semiconductor layer acts as a uniform source of the semiconductor species for diffusion into the semiconductor material in the substrate. In some embodiments, an interlayer is formed between the source semiconductor layer and the substrate, and then the interlayer is trimmed before depositing the source semiconductor layer. In some other embodiments, the source semiconductor layer is deposited directly on the substrate, and has an amorphous or polycrystalline structure.

公开(公告)号：US20180122959A1

公开(公告)日：2018-05-03

申请号：US15726959

申请日：2017-10-06

Applicant: ASM IP Holding B.V.

Inventor： Pauline Calka ,  Qi Xie ,  Dieter Pierreux ,  Bert Jongbloed

IPC: H01L29/792 ,  H01L21/02 ,  H01L27/11524 ,  C23C16/34 ,  H01L29/66 ,  H01L27/11551

CPC classification number: H01L29/792 ,  C23C16/303 ,  C23C16/34 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02227 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0234 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833

Abstract: A semiconductor device and method for manufacturing the semiconductor device are disclosed. Specifically, the semiconductor device may include a charge trapping layer with improved retention and speed for VNAND applications. The charge trapping layer may comprise an aluminum nitride (AlN) or aluminum oxynitride (AlON) layer.

公开(公告)号：US20180122709A1

公开(公告)日：2018-05-03

申请号：US15796593

申请日：2017-10-27

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Michael Eugen Givens ,  Petri Raisanen ,  Jan Willem Maes

IPC: H01L21/8238 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/285 ,  H01L27/092 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823842 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/32133 ,  H01L21/823821 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: Methods for forming a semiconductor device and related semiconductor device structures are provided. In some embodiments, methods may include forming an NMOS gate dielectric and a PMOS gate dielectric over a substrate and forming a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. In some embodiments, methods may also include, removing the first work function metal over the NMOS gate dielectric and forming a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. In some embodiments, related semiconductor device structures may include an NMOS gate dielectric and a PMOS gate dielectric disposed over a semiconductor substrate. A PMOS gate electrode may be disposed over the PMOS gate dielectric and the PMOS gate electrode may include a first work function metal disposed over the PMOS gate dielectric and a second work function metal disposed over the first work function metal. A NMOS gate electrode may be disposed over the NMOS gate dielectric and the NMOS gate electrode may include the second work function metal.

公开(公告)号：US20170317194A1

公开(公告)日：2017-11-02

申请号：US15144506

申请日：2016-05-02

Applicant: ASM IP Holding B.V.

Inventor： Fu Tang ,  Qi Xie ,  Jan Willem Maes ,  Xiaoqiang Jiang ,  Michael Eugene Givens

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66833 ,  H01L21/02112 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/28282

Abstract: A method for forming layers suitable for a V-NAND stack is disclosed. Specifically, the method may include multiple cycles for forming an oxide and a nitride in order to form an oxynitride layer.

公开(公告)号：US09711396B2

公开(公告)日：2017-07-18

申请号：US14741249

申请日：2015-06-16

Applicant: ASM IP Holding B.V.

Inventor： Fu Tang ,  Michael Eugene Givens ,  Jacob Huffman Woodruff ,  Qi Xie ,  Jan Willem Maes

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76829 ,  C23C16/02 ,  C23C16/045 ,  C23C16/305 ,  C23C16/45553 ,  H01L21/02175 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/285 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76895 ,  H01L23/485 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/78

Abstract: In some aspects, methods of forming a metal chalcogenide thin film are provided. According to some methods, a metal chalcogenide thin film is deposited on a substrate in a reaction space in a cyclical deposition process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase chalcogen reactant. In some aspects, methods of forming three-dimensional structure on a substrate surface are provided. In some embodiments, the method includes forming a metal chalcogenide dielectric layer between a substrate and a conductive layer. In some embodiments the method includes forming an MIS-type contact structure including a metal chalcogenide dielectric layer.

公开(公告)号：US20170117203A1

公开(公告)日：2017-04-27

申请号：US15397319

申请日：2017-01-03

Applicant: ASM IP Holding B.V.

Inventor： Fu Tang ,  Michael E. Givens ,  Qi Xie ,  Petri Raisanen

IPC: H01L23/31 ,  C23C16/455 ,  C23C16/44 ,  H01L21/02

CPC classification number: H01L23/3171 ,  C23C16/4405 ,  C23C16/45544 ,  H01L21/02178 ,  H01L21/02205 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/02312 ,  H01L21/306 ,  H01L21/67011 ,  H01L23/02 ,  H01L23/29 ,  H01L23/293 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The method includes providing a high-mobility semiconductor surface to a chamber of a reactor and exposing the high-mobility semiconductor surface to a gas-phase sulfur precursor to passivate the high-mobility semiconductor surface.

公开(公告)号：US20170117202A1

公开(公告)日：2017-04-27

申请号：US15397237

申请日：2017-01-03

Applicant: ASM IP Holding B.V.

Inventor： Fu Tang ,  Michael E. Givens ,  Qi Xie ,  Xiaoqiang Jiang ,  Petri Raisanen ,  Pauline Calka

IPC: H01L23/31 ,  C23C16/40 ,  C23C16/455 ,  H01L21/02 ,  H01L23/29

CPC classification number: H01L23/3171 ,  C23C16/0227 ,  C23C16/0272 ,  C23C16/305 ,  C23C16/40 ,  C23C16/45544 ,  H01L21/02178 ,  H01L21/02205 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/02312 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02664 ,  H01L21/306 ,  H01L23/29 ,  H01L23/291 ,  H01L23/293 ,  H01L28/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The method includes providing a high-mobility semiconductor surface to a chamber of a reactor and exposing the high-mobility semiconductor surface to a gas-phase chalcogen precursor to passivate the high-mobility semiconductor surface.

公开(公告)号：US09558931B2

公开(公告)日：2017-01-31

申请号：US13941216

申请日：2013-07-12

Applicant: ASM IP Holding B.V.

Inventor： Fu Tang ,  Michael Eugene Givens ,  Qi Xie ,  Petri Raisanen

IPC: H01L21/02 ,  H01L23/02 ,  H01L21/67 ,  H01L23/31 ,  H01L23/29 ,  H01L21/306

CPC classification number: H01L23/3171 ,  C23C16/4405 ,  C23C16/45544 ,  H01L21/02178 ,  H01L21/02205 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/02312 ,  H01L21/306 ,  H01L21/67011 ,  H01L23/02 ,  H01L23/29 ,  H01L23/293 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The method includes providing a high-mobility semiconductor surface to a chamber of a reactor and exposing the high-mobility semiconductor surface to a gas-phase sulfur precursor to passivate the high-mobility semiconductor surface.

Abstract translation: 公开了用于钝化高迁移率半导体的表面的改进的方法和系统以及使用这些方法形成的结构和器件。 该方法包括向反应器的室提供高迁移率半导体表面，并将高迁移率半导体表面暴露于气相硫前体以钝化高迁移率半导体表面。