利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

164 条记录 (耗时 0.047 秒)

    Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
    82.
    发明授权
    Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) 失效
    拉伸应变SiGe绝缘体上的应变Si MOSFET（SGOI）

    公开(公告)号：US07217949B2

    公开(公告)日：2007-05-15

    申请号：US10883443

    申请日：2004-07-01

    申请人： Kevin K. Chan ,  Jack O. Chu ,  Kern Rim ,  Leathen Shi

    发明人： Kevin K. Chan ,  Jack O. Chu ,  Kern Rim ,  Leathen Shi

    IPC分类号： H01L29/06

    CPC分类号： H01L29/78687 ,  H01L21/2007 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/78603

    摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

    摘要翻译： 提供了用作形成高性能金属氧化物半导体场效应晶体管（MOSFET）器件的模板的半导体结构。 更具体地，本发明提供一种包括绝缘体上硅衬底的结构，其包括位于绝缘层顶部的拉伸应变SiGe合金层; 以及拉伸应变SiGe合金层顶部的应变Si层。 本发明还提供了形成拉伸应变SGOI基板以及上述异质结构的方法。 本发明的方法通过在绝缘层上直接提供拉伸应变SiGe合金层来分离应变Si层中的高应变和下层中的Ge含量的偏好。

    Bipolar transistor structure with self-aligned raised extrinsic base and methods
    84.
    发明授权
    Bipolar transistor structure with self-aligned raised extrinsic base and methods 有权
    双极晶体管结构具有自对准引出的外在基极和方法

    公开(公告)号：US07037798B2

    公开(公告)日：2006-05-02

    申请号：US10904482

    申请日：2004-11-12

    申请人： Thomas N. Adam ,  Kevin K. Chan ,  Alvin J. Joseph ,  Marwan H. Khater ,  Qizhi Liu ,  Beth Ann Rainey ,  Kathryn T. Schonenberg

    发明人： Thomas N. Adam ,  Kevin K. Chan ,  Alvin J. Joseph ,  Marwan H. Khater ,  Qizhi Liu ,  Beth Ann Rainey ,  Kathryn T. Schonenberg

    IPC分类号： H01L21/331

    CPC分类号： H01L29/7378 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287

    摘要： The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.

    摘要翻译： 本发明包括制造双极晶体管的方法，该双极晶体管在形成连接层之前，将硅锗（SiGe）层或例如高压氧化物（HIPOX）的第三绝缘体层与邻近本征基极的发射极帽顶上相加 。 该添加允许使用湿蚀刻化学去除连接层，以去除在不使用氧化的情况下形成在发射极帽顶上的多余SiGe或第三绝缘体层。 在这种情况下，可以使用氧化物部分（通过沉积氧化物或上述HIPOX层的分离）和氮化物间隔物形成发射极 - 基极隔离。 本发明导致较低的热循环，较低的应力水平和对发射极盖层厚度的更多控制，这是第一实施例的缺点。 本发明还包括所得到的双极晶体管结构。

    Split poly-SiGe/poly-Si alloy gate stack
    85.
    发明授权
    Split poly-SiGe/poly-Si alloy gate stack 有权
    分离多晶硅/多晶硅合金栅叠层

    公开(公告)号：US06927454B2

    公开(公告)日：2005-08-09

    申请号：US10680820

    申请日：2003-10-07

    申请人： Kevin K. Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward J. Nowak

    发明人： Kevin K. Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward J. Nowak

    IPC分类号： H01L20060101 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/49 ,  H01L29/76 ,  H01L31/072 ,  H01L31/119

    CPC分类号： H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

    摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

    摘要翻译： 在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。 硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。 在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4A厚的界面层。 薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻 到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。 栅电极堆叠结构用于nFET和pFET两者。

    Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques
    87.
    发明授权
    Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques 失效
    通过选择性外延和硅晶片结合技术的自对准双栅极MOSFET

    公开(公告)号：US06759710B2

    公开(公告)日：2004-07-06

    申请号：US10051562

    申请日：2002-01-18

    申请人： Kevin K. Chan ,  Guy M. Cohen ,  Yuan Taur ,  Hon-Sum P. Wong

    发明人： Kevin K. Chan ,  Guy M. Cohen ,  Yuan Taur ,  Hon-Sum P. Wong

    IPC分类号： H01L2976

    CPC分类号： H01L29/78654 ,  H01L21/76251 ,  H01L21/76264 ,  H01L21/76275 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78648 ,  H01L29/78684 ,  H01L29/78687 ,  H01L29/78696

    摘要： A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.

    摘要翻译： 制造双栅极金属氧化物半导体晶体管的结构和方法包括在单晶硅沟道的每一侧上形成具有单晶硅沟道层和绝缘氧化物层和氮化物层的叠层结构，在层叠结构中形成开口， 在开口中形成漏极和源极区域，掺杂漏极和源极区域，在层压结构上形成掩模，去除未被掩模保护的层压结构的部分，去除掩模和绝缘氧化物和氮化物层以留下单个 从漏极和源极区域悬置的晶体硅沟道层，形成覆盖漏极和源极区域和沟道层的氧化物层，以及在氧化物层上形成双栅极导体，使得双栅极导体包括第一导体 在单晶硅沟道层的第一侧和在单晶的第二面上的第二导体 l硅通道层。

    Damascene double-gate FET
    88.
    发明授权
    Damascene double-gate FET 有权
    大马士革双栅FET

    公开(公告)号：US06580132B1

    公开(公告)日：2003-06-17

    申请号：US10119799

    申请日：2002-04-10

    申请人： Kevin K. Chan ,  Erin C. Jones ,  Paul M. Solomon ,  Hon-Sum Phillip Wong

    发明人： Kevin K. Chan ,  Erin C. Jones ,  Paul M. Solomon ,  Hon-Sum Phillip Wong

    IPC分类号： H01L2976

    CPC分类号： H01L29/66772 ,  H01L29/4908 ,  H01L29/78648

    摘要： A double-gate field effect transistor (DGFET) is provided using a damascene-like replacement gate processing step to create sidewall source/drain regions, oxide spacers and gate structures inside a previously formed trench. The damascene-like replacement gate processing step allows for the fabrication of a tapered transistor body region having a thicker body under the contacts which reduces access resistance.

    摘要翻译： 使用大马士革式替代栅极处理步骤提供双栅极场效应晶体管（DGFET），以在先前形成的沟槽内部产生侧壁源极/漏极区域，氧化物间隔物和栅极结构。 大马士革式的替代栅极处理步骤允许制造在触点下方具有较厚主体的锥形晶体管主体区域，从而降低访问阻力。

    Method for increasing the capacitance of a trench capacitor
    90.
    发明授权
    Method for increasing the capacitance of a trench capacitor 失效
    增加沟槽电容器电容的方法

    公开(公告)号：US06448131B1

    公开(公告)日：2002-09-10

    申请号：US09929182

    申请日：2001-08-14

    申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy M. Cohen ,  Ramachandra Divakaruni ,  Christian Lavoie ,  Fenton R. McFeely

    发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy M. Cohen ,  Ramachandra Divakaruni ,  Christian Lavoie ,  Fenton R. McFeely

    IPC分类号： H01L218242

    CPC分类号： H01L27/1087 ,  H01L28/84 ,  H01L29/66181 ,  Y10S438/964

    摘要： A method for increasing the trench capacitor surface area is provided. The method, which utilizes a metal silicide to roughen the trench walls, increases capacitance due to the increase in the trench surface area after the silicide has been removed. The roughening of the trench walls can be controlled by varying one or more of the following parameters: the density of the metal, the metal film thickness, the silicide phase, and the choice of the metal. Once the metal is deposited in the trench, the method is self-limited. Shrinking the trench to its original width can be obtained by subsequent silicon deposition or by diffusion of silicon from a cap layer through the silicide.

    摘要翻译： 提供了一种用于增加沟槽电容器表面积的方法。 利用金属硅化物粗糙化沟槽壁的方法由于硅化物被去除之后的沟槽表面积的增加而增加了电容。 可以通过改变一个或多个以下参数来控制沟槽壁的粗糙化：金属的密度，金属膜厚度，硅化物相以及金属的选择。 一旦金属沉积在沟槽中，该方法是自限制的。 通过随后的硅沉积或通过硅化物从盖层扩散硅可以获得将沟槽缩小至原始宽度。