公开(公告)号：US07122824B2

公开(公告)日：2006-10-17

申请号：US10756195

申请日：2004-01-13

申请人： Osama Khouri ,  Giorgio Pollaccia ,  Fabio Pellizzer

发明人： Osama Khouri ,  Giorgio Pollaccia ,  Fabio Pellizzer

IPC分类号： H01L47/00

CPC分类号： H01L45/06 ,  H01L27/2445 ,  H01L45/122 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

摘要： A contact structure for a PCM device is formed by an elongated formation having a longitudinal extension parallel to the upper surface of the body and an end face extending in a vertical plane. The end face is in contact with a bottom portion of an active region of chalcogenic material so that the dimensions of the contact area defined by the end face are determined by the thickness of the elongated formation and by the width thereof.

公开(公告)号：US20060166455A1

公开(公告)日：2006-07-27

申请号：US11042757

申请日：2005-01-25

申请人： George Gordon ,  Stephen Hudgens ,  Fabio Pellizzer ,  Agostino Pirovano

发明人： George Gordon ,  Stephen Hudgens ,  Fabio Pellizzer ,  Agostino Pirovano

IPC分类号： H01L21/20 ,  H01L21/82

CPC分类号： G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/79

摘要： A method for programming a phase change memory cell is disclosed. A phase change memory cell includes a memory element of a phase change material having a first state, in which the phase change material is crystalline and has a minimum resistance level, a second state in which the phase change material is amorphous and has a maximum resistance level, and a plurality of intermediate states, in which the phase change material includes both crystalline regions and amorphous regions and has intermediate resistance levels. According to the method, a plurality of programming pulses are provided to the phase change memory cell; programming energies respectively associated to the programming pulses are lower than a threshold energy which is required to bring the phase change material to the second state.

摘要翻译： 公开了一种用于编程相变存储器单元的方法。 相变存储单元包括具有第一状态的相变材料的存储元件，其中所述相变材料是晶体并且具有最小电阻水平，所述相变材料是非晶态且具有最大电阻的第二状态 电平和多个中间状态，其中相变材料包括结晶区域和非晶区域并具有中等电阻水平。 根据该方法，向相变存储单元提供多个编程脉冲; 分别与编程脉冲相关联的编程能量低于使相变材料进入第二状态所需的阈值能量。

公开(公告)号：US06989580B2

公开(公告)日：2006-01-24

申请号：US10680721

申请日：2003-10-07

申请人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Gastaldi ,  Loris Vendrame ,  Augusto Benvenuti ,  Tyler Lowrey

发明人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Gastaldi ,  Loris Vendrame ,  Augusto Benvenuti ,  Tyler Lowrey

IPC分类号： H01L29/70

CPC分类号： H01L29/685 ,  H01L27/101 ,  H01L27/24

摘要： A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component having a terminal connected to a respective second conduction region.

公开(公告)号：US20050152208A1

公开(公告)日：2005-07-14

申请号：US11045170

申请日：2005-01-27

申请人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

发明人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

IPC分类号： G11C11/56 ,  H01L27/24 ,  H01L45/00 ,  G01R31/08

CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

摘要： A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

摘要翻译： 一种方法使用电阻元件和相变材料的存储区形成相变存储单元。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区域具有第二薄部分，所述第二薄部分具有横向于所述第一尺寸的第二方向的第二亚光刻尺寸。 第一薄部分和第二薄部分直接电接触并限定亚光刻延伸部分的接触面积。 第二薄部分被由限定光刻开口的模具层围绕的氧化物间隔部分侧向限定。 通过间隔物形成技术在形成光刻开口之后形成间隔部分。

公开(公告)号：US20050001284A1

公开(公告)日：2005-01-06

申请号：US10824631

申请日：2004-04-14

申请人： Fabio Pellizzer

发明人： Fabio Pellizzer

IPC分类号： G11C16/02 ,  H01L27/10 ,  H01L45/00 ,  G11B33/02

CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/101 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683 ,  H01L45/1691

摘要： A process for manufacturing a phase change memory cell, comprising the steps of: forming a resistive element; forming a delimiting structure having an aperture over the resistive element; forming a memory portion of a phase change material in the aperture, the resistive element and the memory portion being in direct electrical contact and defining a contact area of sublithographic extension. The step of forming a memory portion further includes filling the aperture with the phase change material and removing from the delimiting structure an exceeding portion of the phase change material exceeding the aperture.

摘要翻译： 一种相变存储单元的制造方法，包括以下步骤：形成电阻元件; 形成在所述电阻元件上具有孔径的限定结构; 在所述孔中形成相变材料的存储部分，所述电阻元件和所述存储器部分直接电接触并限定亚光刻延伸部的接触面积。 形成存储器部分的步骤还包括用相变材料填充孔，并且从限定结构去除超过孔的相变材料的超过部分。

公开(公告)号：US09786719B2

公开(公告)日：2017-10-10

申请号：US13414329

申请日：2012-03-07

申请人： Antonino Rigano ,  Fabio Pellizzer ,  Gianfranco Capetti

发明人： Antonino Rigano ,  Fabio Pellizzer ,  Gianfranco Capetti

IPC分类号： H01L21/70 ,  H01L27/11 ,  H01L27/24 ,  H01L45/00 ,  H01L27/10

CPC分类号： H01L27/2436 ,  H01L27/101 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

摘要： Embodiments disclosed herein may relate to forming a base contact layout in a memory device.

公开(公告)号：US09269747B2

公开(公告)日：2016-02-23

申请号：US13593065

申请日：2012-08-23

申请人： Fabio Pellizzer ,  Antonino Rigano ,  Roberto Somaschini

发明人： Fabio Pellizzer ,  Antonino Rigano ,  Roberto Somaschini

IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311

CPC分类号： H01L21/76897 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/7681 ,  H01L21/76816 ,  H01L23/5226 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.

摘要翻译： 方法和结构提供了从它们延伸的细间距和自对准触点的水平导线，其中触点具有至少一个具有更宽松间距的尺寸。 掩埋硬掩模材料允许线和触点的自对准，而不需要临界掩模，例如用于存储器件中的字线电极线和字线接触。

公开(公告)号：US08964448B2

公开(公告)日：2015-02-24

申请号：US13570772

申请日：2012-08-09

申请人： Ugo Russo ,  Andrea Redaelli ,  Fabio Pellizzer

发明人： Ugo Russo ,  Andrea Redaelli ,  Fabio Pellizzer

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/008 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/16

摘要： Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.

摘要翻译： 具有多个电阻变化材料的电阻变量存储单元及其操作和形成方法在此描述。 作为示例，电阻可变存储单元可以包括位于插塞材料和电极材料之间的多个电阻变化材料。 电阻可变存储单元还包括接触插塞材料和多个电阻可变材料中的每一个的第一导电材料和接触电极材料和多个电阻可变材料中的每一个的第二导电材料。

公开(公告)号：US08785314B2

公开(公告)日：2014-07-22

申请号：US13463245

申请日：2012-05-03

申请人： Fabio Pellizzer ,  Hernan A. Castro ,  Eddie T. Flores

发明人： Fabio Pellizzer ,  Hernan A. Castro ,  Eddie T. Flores

IPC分类号： H01L21/44 ,  H01L21/3213 ,  H01L21/768

CPC分类号： H01L45/1273 ,  H01L21/32134 ,  H01L21/76838 ,  H01L27/101 ,  H01L27/2427 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization includes forming conductive material at respective levels over a substrate. Each respective level of conductive material is electrically coupled to corresponding circuitry on the substrate during patterning of the respective level of conductive material so that each respective level of conductive material has a homogenized etch bias during patterning thereof. Each respective level of conductive material electrically coupled to corresponding circuitry on the substrate is patterned.

摘要翻译： 提供了使用蚀刻偏压均化形成的方法和存储器件。 使用蚀刻偏压均化形成存储器件的一个示例性方法包括在衬底上形成相应电平的导电材料。 在对相应级别的导电材料进行图案化期间，每个相应级别的导电材料电耦合到衬底上的对应电路，使得每个相应级别的导电材料在其图案化期间具有均质化的蚀刻偏压。 电耦合到衬底上的对应电路的每个相应级别的导电材料被图案化。

公开(公告)号：US08766344B2

公开(公告)日：2014-07-01

申请号：US12862624

申请日：2010-08-24

申请人： Fabio Pellizzer ,  Agostino Pirovano

发明人： Fabio Pellizzer ,  Agostino Pirovano

IPC分类号： H01L45/00 ,  G11C13/00

CPC分类号： H01L29/7827 ,  G11C13/0004 ,  H01L27/2454 ,  H01L29/42392 ,  H01L29/665 ,  H01L29/66666 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

摘要： A vertical MOSFET transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first conductivity type; a channel region of a second conductivity type, arranged on top of the buried conductive region; a surface conductive region of the first conductivity type, arranged on top of the channel region and the buried conductive region; a gate insulation region, extending at the sides of and contiguous to the channel region; and a gate region extending at the sides of and contiguous to the gate insulation region.

摘要翻译： 在具有表面的半导体材料的主体中形成垂直MOSFET晶体管。 晶体管包括第一导电类型的掩埋导电区域; 布置在所述掩埋导电区域的顶部上的第二导电类型的沟道区域; 第一导电类型的表面导电区域布置在沟道区域和掩埋导电区域的顶部上; 栅极绝缘区域，在沟道区域的两侧延伸; 以及在栅极绝缘区域的侧面延伸并且与栅极绝缘区域邻接的栅极区域。