公开(公告)号：US10062647B2

公开(公告)日：2018-08-28

申请号：US15646325

申请日：2017-07-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Baozhen Li

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/538 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257

Abstract: Aspects of the present disclosure include interconnect structures for an integrated circuit (IC) structure and methods of making the same. The interconnect structures include one or more electronic devices formed on a substrate. A first interlevel dielectric (ILD) layer is over the one or more electronic devices. The interconnect structure includes a first trench in the first ILD layer. A tungsten contact fills the first trench and is in electrical contact with the one or more electronic devices. A second ILD layer is over the first ILD layer. The interconnect structure includes a second trench in the second ILD layer. Diffusion barrier liners bound all sides of the second trench except at a surface of the tungsten contact. The interconnect structure includes a copper wire filling the second trench, the copper wire in direct contact with the tungsten contact and with the diffusion barrier liners.

公开(公告)号：US10037911B2

公开(公告)日：2018-07-31

申请号：US15692666

申请日：2017-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons ,  Mark D. Jaffe ,  Randy L. Wolf

IPC: H01L21/762 ,  H01L27/13

Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

公开(公告)号：US09929085B2

公开(公告)日：2018-03-27

申请号：US15171320

申请日：2016-06-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. Fitzsimmons ,  Mukta G. Farooq ,  Anthony K. Stamper

IPC: H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/40

Abstract: One aspect of the disclosure relates to an interposer. The interposer may include: a first dielectric layer extending from a substrate in a direction away from a front side of the substrate; a back-end-of-the-line (BEOL) region extending from the substrate in a direction away from the back side of the substrate; a deep trench (DT) capacitor within the substrate and extending toward a back side of the substrate, the DT capacitor having a first portion within the substrate and a second portion within the first dielectric layer; and a through silicon via (TSV) adjacent to the DT capacitor and extending through the first dielectric layer, the substrate, and the BEOL region.

公开(公告)号：US20180005873A1

公开(公告)日：2018-01-04

申请号：US15692666

申请日：2017-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons ,  Mark D. Jaffe ,  Randy L. Wolf

IPC: H01L21/762 ,  H01L27/13

CPC classification number: H01L21/76256 ,  H01L21/6835 ,  H01L21/7624 ,  H01L27/13 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

公开(公告)号：US20170352618A1

公开(公告)日：2017-12-07

申请号：US15171320

申请日：2016-06-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. Fitzsimmons ,  Mukta G. Farooq ,  Anthony K. Stamper

IPC: H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/40

Abstract: One aspect of the disclosure relates to an interposer. The interposer may include: a first dielectric layer extending from a substrate in a direction away from a front side of the substrate; a back-end-of-the-line (BEOL) region extending from the substrate in a direction away from the back side of the substrate; a deep trench (DT) capacitor within the substrate and extending toward a back side of the substrate, the DT capacitor having a first portion within the substrate and a second portion within the first dielectric layer; and a through silicon via (TSV) adjacent to the DT capacitor and extending through the first dielectric layer, the substrate, and the BEOL region.

公开(公告)号：US09806025B2

公开(公告)日：2017-10-31

申请号：US14982097

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons

IPC: H01L21/76 ,  H01L23/532 ,  H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/53238 ,  H01L21/76251 ,  H01L21/76852 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05147

Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

公开(公告)号：US09716136B1

公开(公告)日：2017-07-25

申请号：US15071641

申请日：2016-03-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michel J. Abou-Khalil ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L21/033 ,  H01L21/768 ,  H01L23/525 ,  H01L27/12 ,  H01L49/02

CPC classification number: H01L28/20

Abstract: A method of forming an embedded polysilicon resistor body contact. According to the method, a transistor is formed in and above a crystalline active region that is positioned in a semiconductor layer of a multilayer semiconductor device. A resistor region is defined in single crystal semiconductor material of the semiconductor layer formed on a buried insulating layer. The resistor region is adjacent the transistor. An amorphized semiconductor material is formed in the resistor region. A barrier is formed in the amorphized semiconductor material. The barrier is between the transistor and an electrical body contact for the transistor. The amorphized semiconductor material is annealed, forming a polysilicon semiconductor. The barrier prevents the amorphized region from recrystallizing back to single crystal silicon.

公开(公告)号：US20160372548A1

公开(公告)日：2016-12-22

申请号：US14745764

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hanyi Ding ,  Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L29/73

CPC classification number: H01L29/0813 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/73 ,  H01L29/7371 ,  H01L29/7378

Abstract: Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A base layer comprised of a first semiconductor material is formed. An emitter layer comprised of a second semiconductor material is formed on the base layer. The emitter layer is patterned to form an emitter finger having a length and a width that changes along the length of the emitter finger.

Abstract translation: 用于双极结晶体管的器件结构以及制造用于双极结型晶体管的器件结构的方法。 形成由第一半导体材料构成的基底层。 在基底层上形成由第二半导体材料构成的发射极层。 图案化发射极层以形成发射极指状物，其长度和宽度沿着发射极指的长度而变化。

公开(公告)号：US09524924B2

公开(公告)日：2016-12-20

申请号：US14967965

申请日：2015-12-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel J. Couture ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Anthony K. Stamper

IPC: H01L23/48 ,  H01L21/321 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02125 ,  H01L2224/0226 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/05442

Abstract: An approach to creating a semiconductor structure for a dielectric layer over a void area includes determining a location of a void area of the topographical semiconductor feature. A second dielectric layer is deposited on a first dielectric layer and a top surface of a topographical semiconductor feature. The second dielectric layer is patterned to one or more portions, wherein at least one portion of the patterned second dielectric layer is over the location of the void area of the topographical semiconductor feature. A first metal layer is deposited over the second dielectric layer, at least one portion of the first dielectric layer, and a portion of the top surface of the topographical semiconductor feature. A chemical mechanical polish of the first metal layer is performed, wherein the chemical mechanical polish reaches the top surface of at least one of the one or more portions of the second dielectric layer.

公开(公告)号：US09443764B2

公开(公告)日：2016-09-13

申请号：US14052366

申请日：2013-10-11

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Jeffrey C. Maling ,  Anthony K. Stamper ,  Zeljka Topic-Beganovic ,  Daniel S. Vanslette

IPC: H01L21/768 ,  H05K1/11 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H05K1/115 ,  H01L2924/00

Abstract: A method and structure for eliminating through silicon via poor reveal is disclosed. In one embodiment, the method includes obtaining a wafer having a front side, a back side and partially etched and metalized through silicon vias each extending from a portion of the front side through a portion of the back side, terminating before reaching an end surface of the back side. A region of the back side of the wafer is patterned and etched to expose and reveal a portion of each of the plurality of through silicon vias. A metal layer is deposited on the back side of the wafer to form a back side metallization. The metal layer covers all of the back side including the etched region of the back side and the exposed portions of each of the through silicon vias.

Abstract translation: 公开了一种通过不良露出来消除硅的方法和结构。 在一个实施例中，该方法包括获得具有正面，背面以及通过硅通孔部分蚀刻和金属化的晶片，每个硅通孔从前侧的一部分延伸穿过后侧的一部分，在到达 背面。 对晶片的背面的区域进行图案化和蚀刻，以暴露和显露多个通孔中的每个通孔的一部分。 金属层沉积在晶片的背面以形成背面金属化。 金属层覆盖包括后侧的蚀刻区域和通孔硅通孔中的每一个的暴露部分的所有背面。