公开(公告)号：US08513722B2

公开(公告)日：2013-08-20

申请号：US12715843

申请日：2010-03-02

申请人： Sanh D. Tang ,  John K. Zahurak ,  Werner Juengling

发明人： Sanh D. Tang ,  John K. Zahurak ,  Werner Juengling

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10802 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/4236 ,  H01L29/7841

摘要： Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed.

摘要翻译： 包括浮置体细胞结构，其包括布置在背栅上的浮体阵列阵列和与后门间隔开的浮体细胞的源区和漏区。 浮体细胞可以各自包括体积的半导体材料，其具有在柱之间延伸的通道区域，其可以通过诸如U形沟槽的空隙分开。 阵列的浮体电池可以电耦合到另一个栅极，另一个栅极可以设置在半导体材料的体积的侧壁上或其内的空隙中。 还公开了形成浮体电池器件的方法。

公开(公告)号：US08501559B2

公开(公告)日：2013-08-06

申请号：US13610513

申请日：2012-09-11

申请人： Sanh D. Tang ,  John K. Zahurak

发明人： Sanh D. Tang ,  John K. Zahurak

IPC分类号： H01L21/8234

CPC分类号： H01L21/762 ,  H01L21/32 ,  H01L27/0814 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/2454 ,  H01L27/2472 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/861 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.

公开(公告)号：US20130005100A1

公开(公告)日：2013-01-03

申请号：US13610513

申请日：2012-09-11

申请人： Sanh D. Tang ,  John K. Zahurak

发明人： Sanh D. Tang ,  John K. Zahurak

IPC分类号： H01L21/336

CPC分类号： H01L21/762 ,  H01L21/32 ,  H01L27/0814 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/2454 ,  H01L27/2472 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/861 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.

公开(公告)号：US20120217564A1

公开(公告)日：2012-08-30

申请号：US13035700

申请日：2011-02-25

申请人： Sanh D. Tang ,  John K. Zahurak

发明人： Sanh D. Tang ,  John K. Zahurak

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  B82Y99/00

CPC分类号： H01L27/11556 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/167 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

摘要： Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.

摘要翻译： 描述形成多层半导体器件的方法以及包括它们的装置和系统。 在一种这样的方法中，在半导体材料层和电介质层中形成开口。 通过开口暴露的半导体材料层的一部分被处理，使得该部分与该层中剩余的半导体材料不同地掺杂。 至少基本上所有剩余的层的半导体材料被去除，留下半导体材料层的不同掺杂部分作为电荷存储结构。 在电荷存储结构的第一表面上形成隧道电介质，并且在电荷存储结构的第二表面上形成隔间电介质。 还描述了另外的实施例。

公开(公告)号：US20110215408A1

公开(公告)日：2011-09-08

申请号：US12715843

申请日：2010-03-02

申请人： Sanh D. Tang ,  John K. Zahurak ,  Werner Juengling

发明人： Sanh D. Tang ,  John K. Zahurak ,  Werner Juengling

IPC分类号： H01L29/786

CPC分类号： H01L27/10802 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/4236 ,  H01L29/7841

摘要： Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed.

摘要翻译： 包括浮置体细胞结构，其包括布置在背栅上的浮体阵列阵列和与后门间隔开的浮体细胞的源区和漏区。 浮体细胞可以各自包括体积的半导体材料，其具有在柱之间延伸的通道区域，其可以通过诸如U形沟槽的空隙分开。 阵列的浮体电池可以电耦合到另一个栅极，另一个栅极可以设置在半导体材料的体积的侧壁上或其内的空隙中。 还公开了形成浮体电池器件的方法。

公开(公告)号：US07718495B2

公开(公告)日：2010-05-18

申请号：US11849813

申请日：2007-09-04

申请人： Kunal R. Parekh ,  John K. Zahurak

发明人： Kunal R. Parekh ,  John K. Zahurak

IPC分类号： H01L21/00

CPC分类号： H01L21/823468 ,  H01L21/823418 ,  H01L21/823425 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11534

摘要： The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.

摘要翻译： 本发明包括形成集成电路的方法，形成存储器电路的方法以及形成场效应晶体管的方法。 在一个实施方案中，导电金属硅化物形成在衬底的一些区域上而不是其它区域上。 在一个实施方案中，导电金属硅化物形成在晶体管源极/漏极区上，并且与在晶体管的栅极附近的各向异性蚀刻的侧壁间隔开。

公开(公告)号：US20090176338A1

公开(公告)日：2009-07-09

申请号：US12401555

申请日：2009-03-10

申请人： Hongmei Wang ,  John K. Zahurak

发明人： Hongmei Wang ,  John K. Zahurak

IPC分类号： H01L21/84

CPC分类号： H01L29/4908 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/78621

摘要： A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.

摘要翻译： 公开了一种完全耗尽（FD）的绝缘体上硅（SOI）MOSFET存取晶体管，其包括与源/漏区的导电类型相反的导电类型的栅电极和制造方法。

公开(公告)号：US20080265340A1

公开(公告)日：2008-10-30

申请号：US12170786

申请日：2008-07-10

申请人： Byron Neville Burgess ,  John K. Zahurak

发明人： Byron Neville Burgess ,  John K. Zahurak

IPC分类号： H01L27/088

CPC分类号： H01L21/76897 ,  H01L21/0332 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/1052 ,  H01L27/1085 ,  H01L27/10888 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

摘要： Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.

摘要翻译： 公开了用于在集成电路中形成触点的牺牲插头以及在集成电路阵列中形成连接的方法。 可以使用各种图案转移和蚀刻步骤来创建密集堆叠的特征以及特征之间的连接。 牺牲材料可以以跨越字线的连续的之字形线图案被图案化。 平面化可以产生平行四边形的材料块，其可以覆盖有源区域以形成牺牲插塞，其可以用导电材料代替以形成接触。

公开(公告)号：US07419913B2

公开(公告)日：2008-09-02

申请号：US11217905

申请日：2005-09-01

申请人： Thomas M. Graettinger ,  John K. Zahurak ,  Shane J. Trapp ,  Thomas Arthur Figura

发明人： Thomas M. Graettinger ,  John K. Zahurak ,  Shane J. Trapp ,  Thomas Arthur Figura

IPC分类号： H01L21/461

CPC分类号： H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76844 ,  H01L27/10852

摘要： This invention includes methods of forming openings into dielectric material. In one implementation, an opening is partially etched through dielectric material, with such opening comprising a lowest point and opposing sidewalls of the dielectric material. At least respective portions of the opposing sidewalls within the opening are lined with an electrically conductive material. With such electrically conductive material over said respective portions within the opening, plasma etching is conducted into and through the lowest point of the dielectric material of the opening to extend the opening deeper within the dielectric material. Other aspects and implementations are contemplated.

摘要翻译： 本发明包括在电介质材料中形成开口的方法。 在一个实施方案中，通过电介质材料部分蚀刻开口，其中这种开口包括介电材料的最低点和相对的侧壁。 开口内的相对侧壁的至少相应部分衬有导电材料。 通过在开口内的所述各个部分上的这种导电材料，等离子体蚀刻被导入并通过开口的电介质材料的最低点，以使电介质材料内的开口更深。 考虑了其他方面和实现。

公开(公告)号：US07399671B2

公开(公告)日：2008-07-15

申请号：US11217980

申请日：2005-09-01

申请人： Byron Neville Burgess ,  John K. Zahurak

发明人： Byron Neville Burgess ,  John K. Zahurak

IPC分类号： H01L21/8242

CPC分类号： H01L21/76897 ,  H01L21/0332 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/1052 ,  H01L27/1085 ,  H01L27/10888 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

摘要： Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.

摘要翻译： 公开了用于在集成电路中形成触点的牺牲插头以及在集成电路阵列中形成连接的方法。 可以使用各种图案转移和蚀刻步骤来创建密集堆叠的特征以及特征之间的连接。 牺牲材料可以以跨越字线的连续的之字形线图案被图案化。 平面化可以产生平行四边形的材料块，其可以覆盖有源区域以形成牺牲插塞，其可以用导电材料代替以形成接触。