公开(公告)号：US10236041B2

公开(公告)日：2019-03-19

申请号：US15597846

申请日：2017-05-17

Applicant: Infineon Technologies AG

Inventor： Mihail Jefremow ,  Thomas Kern ,  Christian Peters

IPC: G11C7/22 ,  G11C7/06 ,  G11C13/00 ,  G11C16/26 ,  G11C16/28 ,  G11C16/32

Abstract: A method is suggested for determining a state of a memory cell via a sense amplifier the method including applying a first signal to the sense amplifier; sensing a first response; determining a reference signal based on the first signal; sensing a second response based on a second signal that is determined based on the first signal; and determining the state of the memory cell based on the second response and the reference signal. Also, a memory device that is able to determine the state of the memory cell is provided.

公开(公告)号：US10216573B2

公开(公告)日：2019-02-26

申请号：US15410912

申请日：2017-01-20

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Michael Goessel ,  Karl Hofmann

IPC: H03M13/00 ,  G06F11/10 ,  G11C29/52 ,  H03M13/15 ,  H03M13/29 ,  G11C29/04

Abstract: In various embodiments, a method of correcting and/or detecting an error in a memory device is provided. The method may include, in a first operations mode, applying a first code to detect and/or correct an error, and in a second operations mode after an inactive mode and before entering the first operations mode, applying a second code for correcting and/or detecting an error, wherein the first code and the second code have different code words.

公开(公告)号：US10067826B2

公开(公告)日：2018-09-04

申请号：US15194089

申请日：2016-06-27

Applicant: Infineon Technologies AG

Inventor： Thomas Rabenalt ,  Ulrich Backhausen ,  Thomas Kern ,  Michael Goessel

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/13 ,  G06F3/06 ,  G11C16/10 ,  G11C16/26 ,  G11C29/04

Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.

公开(公告)号：US20180190333A1

公开(公告)日：2018-07-05

申请号：US15597846

申请日：2017-05-17

Applicant: Infineon Technologies AG

Inventor： Mihail Jefremow ,  Thomas Kern ,  Christian Peters

IPC: G11C7/22 ,  G11C7/06

CPC classification number: G11C7/22 ,  G11C7/06 ,  G11C7/065 ,  G11C7/067 ,  G11C13/004 ,  G11C13/0061 ,  G11C16/26 ,  G11C16/28 ,  G11C16/32 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2207/063 ,  G11C2207/068 ,  G11C2213/79

Abstract: A method is suggested for determining a state of a memory cell via a sense amplifier the method including applying a first signal to the sense amplifier; sensing a first response; determining a reference signal based on the first signal; sensing a second response based on a second signal that is determined based on the first signal; and determining the state of the memory cell based on the second response and the reference signal. Also, a memory device that is able to determine the state of the memory cell is provided.

公开(公告)号：US20170046222A1

公开(公告)日：2017-02-16

申请号：US15232323

申请日：2016-08-09

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Michael Goessel

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1044 ,  G11C17/146 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A method is proposed for storing bits in memory cells of a memory, wherein in two successive write operations first and second wits are written to identical memory cells at an identical address, without the memory cells being erased after the first write operation, wherein first check bits are stored in further first memory cells and second check bits are stored in further second memory cells. A corresponding device is furthermore specified.

Abstract translation: 提出了一种用于存储存储器的存储单元中的位的方法，其中在两个连续的写入操作中，第一和第二存储单元以相同的地址被写入相同的存储器单元，而在第一写操作之后不擦除存储单元，其中第一次检查 位存储在另外的第一存储器单元中，并且第二校验位存储在另外的第二存储器单元中。 此外指定相应的装置。

公开(公告)号：US09520161B2

公开(公告)日：2016-12-13

申请号：US14834897

申请日：2015-08-25

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Michael Goessel ,  Karl Hofmann

IPC: G11C5/06 ,  G11C11/56 ,  G11C7/22 ,  G11C7/14 ,  G11C16/28

CPC classification number: G11C5/06 ,  G11C7/14 ,  G11C7/22 ,  G11C11/5642 ,  G11C16/28

Abstract: A method and associated apparatus to determine a reference value on the basis of a plurality of half reference values stored in memory cells is disclosed, wherein the plurality of half reference values are read from the memory cells, wherein a subset of half reference values is determined from the plurality of half reference values, and wherein the reference value is determined on the basis of the subset of half reference values.

Abstract translation: 公开了一种基于存储在存储器单元中的多个半参考值来确定参考值的方法和相关设备，其中从存储器单元读取多个半参考值，其中确定半参考值的子集 从所述多个半参考值中，并且其中所述参考值基于所述半参考值的子集来确定。

公开(公告)号：US20160306696A1

公开(公告)日：2016-10-20

申请号：US15194089

申请日：2016-06-27

Applicant: Infineon Technologies AG

Inventor： Thomas Rabenalt ,  Ulrich Backhausen ,  Thomas Kern ,  Michael Goessel

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1012 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/13

Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.

Abstract translation: 公开了一种用于访问非易失性存储器的方法和存储器控制器。 该方法包括读取非易失性存储器的第一存储器区域，确定第一存储器区域是否包含预定数据模式，其中预定数据模式对至少第一存储器区域确定的所得到的纠错数据没有影响。 该方法基于第一存储器区域中的预定数据模式的存在来评估非易失性存储器的第二存储器区域的数据状态，其中数据状态指示是否存在有效数据中的至少一个 第二存储器区域以及第二存储器区域是否可写入。

公开(公告)号：US09460759B2

公开(公告)日：2016-10-04

申请号：US14149353

申请日：2014-01-07

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Mihail Jefremow

IPC: G11C7/12 ,  G11C7/06 ,  G11C11/16 ,  G11C13/00 ,  G11C16/26

CPC classification number: G11C7/062 ,  G11C7/12 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/004 ,  G11C16/26

Abstract: A sense amplifier of a memory cell having a sense voltage generating circuit configured to generate a sense voltage; and a sensing circuit configured to compare a bitline voltage of the memory cell with the sense voltage, and to output a digital output signal indicating a content of the memory cell, wherein during a sense phase, the sensing circuit is decoupled from a voltage supply which charges a bitline capacitance during a precharge phase, and is coupled to and supplied by the bitline capacitance. The sense voltage generating circuit may be further configured to generate a sense voltage that during a precharge phase is dependent on the voltage supply and during a sense phase is independent of the voltage supply.

Abstract translation: 具有感测电压发生电路的存储单元的读出放大器被配置为产生检测电压; 以及感测电路，被配置为将存储器单元的位线电压与感测电压进行比较，并且输出指示存储器单元的内容的数字输出信号，其中在感测阶段期间，感测电路与电压源 在预充电阶段期间对位线电容充电，并且被位线电容耦合并由位线电容提供。 感测电压产生电路还可以被配置为产生在预充电阶段期间取决于电压供应并且在感测阶段期间独立于电压供应的感测电压。

公开(公告)号：US20160172029A1

公开(公告)日：2016-06-16

申请号：US14570219

申请日：2014-12-15

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Karl Hofmann ,  Michael Goessel

IPC: G11C13/00 ,  G11C29/52 ,  G11C29/00 ,  G06F11/10 ,  G11C11/16 ,  G11C29/08

CPC classification number: G11C29/76 ,  G06F11/1048 ,  G06F11/106 ,  G11C7/04 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0033 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50016 ,  G11C29/52 ,  H03M13/3715

Abstract: A system and method of refreshing a nonvolatile memory having memory cells. The method includes identifying one or more of the memory cells that do not satisfy a data retention test; remapping the one or more identified memory cells from original memory addresses to spare memory addresses; and refreshing the identified memory cells.

Abstract translation: 一种刷新具有存储单元的非易失性存储器的系统和方法。 该方法包括识别不满足数据保留测试的一个或多个存储器单元; 将一个或多个所识别的存储器单元从原始存储器地址重新映射到备用存储器地址; 并刷新所识别的存储器单元。

公开(公告)号：US09196320B2

公开(公告)日：2015-11-24

申请号：US14106277

申请日：2013-12-13

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Mihail Jefremow

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C7/1006 ,  G11C7/1069 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/004 ,  G11C16/28 ,  G11C2013/0042

Abstract: An embodiment relates to a method for data processing and comprises determining an electrical variable for each cell of a data bit, transforming each electrical variable into the time domain, and determining a blank state for at least one data bit based on a comparison of the transformed electrical variables.

Abstract translation: 一个实施例涉及一种用于数据处理的方法，包括：确定数据位的每个单元的电变量，将每个电变量变换成时域，以及根据变换后的变量的比较确定至少一个数据位的空白状态 电气变量。