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公开(公告)号：US20170236580A1
公开(公告)日：2017-08-17
申请号：US15046339
申请日：2016-02-17
Applicant: Intel Corporation
Inventor： Daniel Chu , Kiran Pangal , Mase Taub , Sandeep Guliani , Raymond Zeng
IPC: G11C13/00
Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including dual demarcation voltage sensing before writes.
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公开(公告)号：US09685213B2
公开(公告)日：2017-06-20
申请号：US15347736
申请日：2016-11-09
Applicant: Intel Corporation
Inventor： Dany-Sebastien Ly-Gagnon , Kiran Pangal , Raymond W. Zeng , Mase J. Taub
CPC classification number: G11C11/00 , G06F11/1048 , G11C7/04 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0045 , G11C2013/0078 , G11C2013/0092 , G11C2213/77 , H01L29/06 , H04L65/403
Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.
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83.发明授权公开(公告)号：US09613698B2
公开(公告)日：2017-04-04
申请号：US15154465
申请日：2016-05-13
Applicant: INTEL CORPORATION
Inventor： Davide Mantegazza , Kiran Pangal , Gerard H. Joyce , Prashant Damle , Derchang Kau , Davide Fugazza
IPC: G11C13/00
CPC classification number: G11C13/0097 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0092
Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In an embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device, wherein the memory cell is coupled with a capacitor and subsequent to said increasing the current, generating a transient current through the memory cell by discharge of the capacitor to reset the memory cell. In another embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device and controlling the current to be greater than a threshold current and lower than a hold current of the memory cell to set the memory cell. Other embodiments may be described and/or claimed.
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公开(公告)号：US09583187B2
公开(公告)日：2017-02-28
申请号：US14672130
申请日：2015-03-28
Applicant: Intel Corporation
Inventor： Sanjay Rangan , Kiran Pangal , Nevil N Gajera , Lu Liu , Gayathri Rao Subbu
CPC classification number: G11C13/0069 , G11C7/04 , G11C11/16 , G11C13/0004 , G11C13/0061 , G11C2013/0078 , G11C2013/008 , G11C2013/0092 , H01L45/06 , H01L45/1286 , H01L45/141
Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.
Abstract translation: 相变材料可以通过多级设定过程进行设置。 设置控制逻辑可以将相变半导体材料（PM）加热到第一温度一段时间。 第一温度被配置成促进PM的结晶状态的成核。 控制逻辑可以将温度升高到第二温度持续第二时间段。 第二温度被配置为促进PM内的晶体生长。 晶体的成核和生长将PM设置为结晶状态。 相对于传统方法，多级升温可以提高设定过程的效率。
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公开(公告)号：US20160372194A1
公开(公告)日：2016-12-22
申请号：US14742316
申请日：2015-06-17
Applicant: Intel Corporation
Inventor： Dany-Sebastien Ly-Gagnon , Kiran Pangal , Raymond W. Zeng , Mase J. Taub
IPC: G11C13/00
CPC classification number: G11C11/00 , G06F11/1048 , G11C7/04 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0045 , G11C2013/0078 , G11C2013/0092 , G11C2213/77 , H01L29/06 , H04L65/403
Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例描述了用于控制非易失性随机存取存储器（NVRAM）设备中的电流的技术和配置。 在一个实施例中，NVRAM器件可以包括耦合到多个位线的多个存储器单元，其形成具有寄生电容的位线节点。 每个存储器单元可以包括具有保持电流的所需电平的开关器件，以保持电池的导通状态。 电压供应电路和控制器可以与NVRAM器件耦合。 控制器可以控制电路以提供使存储器单元处于导通状态的电流脉冲。 响应于在实现设定点之后通过存储器单元的位线节点电容的放电，脉冲可以包括随时间从设定点改变到保持电流电平的分布。 可以描述和/或要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US20160357458A1
公开(公告)日：2016-12-08
申请号：US15076963
申请日：2016-03-22
Applicant: Intel Corporation
Inventor： Kiran Pangal , Ravi J. Kumar
CPC classification number: G06F3/0616 , G06F3/064 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G06F11/2094 , G11C11/5635 , G11C11/5642 , G11C16/00 , G11C16/14 , G11C16/26 , G11C16/3436 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/50016 , G11C29/52 , G11C2029/0401
Abstract: Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.
Abstract translation: 描述了提供动态窗口以提高NAND（Not And）存储器耐久性的方法和装置。 在一个实施例中，与NAND存储器件相关联的编程擦除窗口通过从较高的擦除验证（TEV）电压开始并基于当前周期在NAND存储器件的使用寿命内随后的周期降低TEV电压而动态地改变 计数值。 或者，通过以更高的擦除验证（PV）电压和擦除验证（TEV）电压开始，并且基于当前的NAND存储器件的使用寿命期间的随后的周期来降低PV和TEV电压，编程擦除窗口被动态变化 循环计数值。 还公开并要求保护其他实施例。
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公开(公告)号：US09437293B1
公开(公告)日：2016-09-06
申请号：US14671471
申请日：2015-03-27
Applicant: Intel Corporation
Inventor： Arjun Kripanidhi , Kiran Pangal , Lark-Hoon Leem , Balaji Srinivasan
CPC classification number: G11C13/0033 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0047 , G11C2013/0052 , G11C2013/0066
Abstract: Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus includes read circuitry to apply a read voltage to a phase change memory (PCM) cell, setback circuitry to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is configured to transition the PCM cell from an amorphous state to a crystalline state, sense circuitry to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例描述了在相变存储器中的读取和写入操作以减少突发干扰。 在一个实施例中，一种装置包括读取电路，用于将读取电压施加到相变存储器（PCM）单元，响应于读取电压的应用，将回退脉冲施加到PCM单元，其中挫折脉冲是 对于被配置为将PCM单元从非晶状态转换为结晶状态的规则设定脉冲，对于比第二时间段短的第一时间段执行的更短的设定脉冲，感测电路与应用同时感测 的挫折脉冲，PCM单元是处于非晶态还是结晶状态。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US09384831B2
公开(公告)日：2016-07-05
申请号：US14289858
申请日：2014-05-29
Applicant: Intel Corporation
Inventor： Mase J Taub , Sandeep K. Guliani , Kiran Pangal
CPC classification number: G11C13/0004 , G11C5/02 , G11C7/00 , G11C13/004 , G11C13/0069 , G11C2013/0076 , G11C2013/0078 , G11C2013/0092 , G11C2213/77
Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.
Abstract translation: 公开了用于在交叉点存储器中写入数据的系统和技术。 检测交叉点存储器的一个或多个存储单元的状态，然后继续选择并保持。 然后，基于要写入一个或多个存储器单元的输入用户数据，确定一个或多个存储器单元中的哪一个将改变状态。 然后通过向存储器单元施加写入电流脉冲来写入确定为改变状态并且仍被选择为导通的一个或多个存储器单元。 在一个示例性实施例中，一个或多个存储器单元包括一个或多个相变型存储单元器件。
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公开(公告)号：US20160085621A1
公开(公告)日：2016-03-24
申请号：US14493956
申请日：2014-09-23
Applicant: Intel Corporation
Inventor： Ravi H. Motwani , Kiran Pangal
CPC classification number: G06F11/1008 , G06F11/10 , G06F11/1068 , G06F11/108 , G06F12/0246 , G11C29/52 , G11C2029/0411 , H03M13/1108
Abstract: Apparatus, systems, and methods for Recovery algorithm in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device to read a line of data to the memory device, wherein the data is spread across a plurality (N) of dies and comprises an error correction code (ECC) spread across the plurality (N) of dies, retrieve the line of data from the memory device, perform an error correction code (ECC) check on the line of data retrieved from the memory device, and invoke a recovery algorithm in response to an error in the ECC check on the line of data retrieved from the memory device. Other embodiments are also disclosed and claimed.
Abstract translation: 描述了存储器中恢复算法的装置，系统和方法。 在一个实施例中，控制器包括用于接收来自主机设备的读请求以读取到存储器设备的数据线的逻辑，其中数据分布在多个（N）个管芯上，并且包括纠错码（ECC） 分布在多个（N）个管芯上，从存储器件检索数据线，对从存储器件检索的数据行执行纠错码（ECC）校验，并响应错误调用恢复算法 在ECC中检查从存储器件检索的数据行。 还公开并要求保护其他实施例。
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公开(公告)号：US09286975B2
公开(公告)日：2016-03-15
申请号：US14204376
申请日：2014-03-11
Applicant: Intel Corporation
Inventor： Daniel J. Chu , Kiran Pangal , Nathan R. Franklin , Prashant S. Damle , Hu Chaohong
CPC classification number: G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/0035 , G11C13/0061 , G11C2013/0047 , G11C2013/0052
Abstract: The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.
Abstract translation: 本公开涉及减轻交叉点存储器中的读取干扰。 设备可以包括被配置为选择用于存储器访问操作的目标存储器单元的存储器控制器。 存储器控制器包括感测模块，其被配置为确定在感测间隔期间是否发生快照事件; 以及写回模块，被配置为如果检测到快照事件，则将逻辑1写回到所述存储器单元。
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