公开(公告)号：US09882048B2

公开(公告)日：2018-01-30

申请号：US15197996

申请日：2016-06-30

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Sivananda K. Kanakasabapathy ,  Jeffrey C. Shearer ,  Stuart A. Sieg ,  John R. Sporre ,  Junli Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/49

CPC classification number: H01L29/7827 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer is patterned onto the memorization layer. An anti-reflective coating layer is patterned onto the planarizing layer. A photoresist layer is patterned onto the anti-reflective coating layer on ends of fins extending from a substrate. The planarizing layer, the anti-reflective coating layer, and the photoresist form a mask. The anti-reflective coating layer portion is etched from the VFET. The planarizing layer and the photoresist layer are arc etched from the VFET. The spacer is pulled down forming a void between gates on the VFET and exposing a hard mask on the fins. The hard mask is reactive ion etched vertically around the gates to form gates with a defined width mask. The memorization layer is removed from the VFET.

公开(公告)号：US20170330753A1

公开(公告)日：2017-11-16

申请号：US15153226

申请日：2016-05-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/033 ,  H01L29/66

CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/32105 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: Methods of forming semiconductor fins include forming first spacers on a first sidewall of each of a plurality of mandrels using an angled deposition process. A second sidewall of one or more of the plurality of mandrels is masked. Second spacers are formed on a second sidewall of all unmasked mandrels. The second sidewall of the one or more of the plurality of mandrels is unmasked. The mandrels are etched away. Fins are formed from a substrate using the first and second spacers as a mask.

公开(公告)号：US20170222024A1

公开(公告)日：2017-08-03

申请号：US15368089

申请日：2016-12-02

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  Jeffrey C. Shearer ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/66 ,  H01L21/3065 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66742 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.

公开(公告)号：US20170221773A1

公开(公告)日：2017-08-03

申请号：US15489303

申请日：2017-04-17

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ryan O. Jung ,  Fee Li Lie ,  Eric R. Miller ,  Jeffrey C. Shearer ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/84 ,  H01L21/308 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/311

Abstract: A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin that is employed has a same pitch as the pitch of each semiconductor fin and the same height as the dielectric spacers on the sidewalls of each semiconductor fin. Exposed portions of the sacrificial spacer fin are removed simultaneously during a dielectric spacer reactive ion etch (RIE). The presence of the sacrificial spacer fin improves the endpoint detection of the spacer RIE and increases the endpoint signal intensity.

公开(公告)号：US09721848B1

公开(公告)日：2017-08-01

申请号：US15337189

申请日：2016-10-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huiming Bu ,  Kangguo Cheng ,  Andrew M. Greene ,  Dechao Guo ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Balasubramanian S. Pranatharthiharan ,  Stuart A. Sieg ,  John R. Sporre ,  Gen Tsutsui ,  Rajasekhar Venigalla ,  Huimei Zhou

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/823878 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device includes a first fin and a second fin arranged on a substrate, a gate stack arranged over a channel region of the first fin, and spacers arranged along sidewalls of the gate stack. A cavity is arranged adjacent to a distal end of the gate stack. The cavity is defined by the substrate, a distal end of the second fin, and the spacers. A dielectric fill material is arranged in the cavity such that the dielectric fill material contacts the substrate, the distal end of the second fin, and the spacers.

公开(公告)号：US20170162685A1

公开(公告)日：2017-06-08

申请号：US14956711

申请日：2015-12-02

Applicant: International Business Machines Corporation

Inventor： Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Juntao Li ,  Fee Li Lie ,  Stuart A. Sieg ,  John R. Sporre

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L29/06

CPC classification number: H01L29/6681 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/785

Abstract: Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.

公开(公告)号：US09620590B1

公开(公告)日：2017-04-11

申请号：US15270109

申请日：2016-09-20

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/00 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L21/308 ,  H01L29/66 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/31111 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78696

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

公开(公告)号：US11004944B2

公开(公告)日：2021-05-11

申请号：US16682361

申请日：2019-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Andrew M. Greene ,  John R. Sporre ,  Peng Xu

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/775

Abstract: Methods of forming semiconductor devices include forming a lower dielectric layer, to a height below a height of a dummy gate hardmask disposed across multiple device regions, by forming a dielectric fill to the height of a dummy gate and etching the dielectric fill back. A dummy gate structure includes the dummy gate and the dummy gate hardmask. A protective layer is formed on the dielectric layer to the height of the dummy gate hardmask. The dummy gate hardmask is etched back to expose the dummy gate.

公开(公告)号：US20200144495A1

公开(公告)日：2020-05-07

申请号：US16734922

申请日：2020-01-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony J. Annunziata ,  Babar A. Khan ,  Chandrasekharan Kothandaraman ,  John R. Sporre

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  G11C11/16

Abstract: Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.

公开(公告)号：US10573745B2

公开(公告)日：2020-02-25

申请号：US15602884

申请日：2017-05-23

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/78 ,  H01L29/66

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.