公开(公告)号：US09525064B1

公开(公告)日：2016-12-20

申请号：US14970977

申请日：2015-12-16

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: A method of making a vertical transistor includes forming a doped source on a substrate; depositing a sacrificial gate material on the source; forming a trench in the sacrificial gate material to expose the doped source; growing an epitaxial layer within the trench to form a channel region extending from the doped source and through the sacrificial gate material; performing an epitaxial growth process to grow an epitaxial layer on a portion of the channel region to form a drain over the sacrificial gate material; depositing a dielectric material on the drain to form a spacer that protects the epitaxial growth; and removing the sacrificial gate material and replacing the sacrificial gate material with a gate stack that surrounds the channel region between the doped source and the drain.

Abstract translation: 制造垂直晶体管的方法包括在衬底上形成掺杂源; 在源上沉积牺牲栅极材料; 在所述牺牲栅极材料中形成沟槽以暴露所述掺杂源; 在沟槽内生长外延层以形成从掺杂源延伸并穿过牺牲栅极材料的沟道区; 执行外延生长工艺以在所述沟道区域的一部分上生长外延层，以在所述牺牲栅极材料上形成漏极; 在漏极上沉积介电材料以形成保护外延生长的间隔物; 以及去除牺牲栅极材料并用围绕掺杂源极和漏极之间的沟道区域的栅极堆叠代替牺牲栅极材料。

公开(公告)号：US20160359045A1

公开(公告)日：2016-12-08

申请号：US14732840

申请日：2015-06-08

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/7851

Abstract: A semiconductor device includes at least one semiconductor fin on an upper surface of a base substrate. The at least one semiconductor fin includes a strained active semiconductor portion interposed between a protective cap layer and the base substrate. A gate stack wraps around the at least one semiconductor fin. The gate stack includes a metal gate element interposed between a pair of first cap segments of the protective cap layer. The strained active semiconductor portion is preserved following formation of the fin via the protective cap layer.

公开(公告)号：US20160358823A1

公开(公告)日：2016-12-08

申请号：US14743561

申请日：2015-06-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/08 ,  H01L21/308 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/0337 ,  H01L21/308 ,  H01L21/76877 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain regions are formed on opposite ends of the pair of fins and include silicon. A gate is wrapped around the pair of fins, between the source and drain regions.

Abstract translation: 在一个示例中，场效应晶体管包括以间隔开的关系定位的一对鳍片。 每个翅片包括锗。 源极和漏极区域形成在一对鳍片的相对端上并且包括硅。 在一对鳍片之间，在源极和漏极区域之间缠绕栅极。

公开(公告)号：US09515194B2

公开(公告)日：2016-12-06

申请号：US14670588

申请日：2015-03-27

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/0665 ,  H01L21/30612 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1087 ,  H01L29/20 ,  H01L29/423 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78681 ,  H01L29/78696

Abstract: Embodiments of the invention include a method for fabricating a nano-ribbon transistor device and the resulting structure. A nano-ribbon transistor device including a substrate, a nano-ribbon channel, a core region in the center of the nano-ribbon channel, a gate formed around the nano-ribbon channel, a spacer formed on each sidewall of the gate, and a source and drain region epitaxially formed adjacent to each spacer is provided. The core region in the center of the nano-ribbon channel is selectively etched. A dielectric material is deposited on the exposed portions of the nano-ribbon channel. A back-bias control region is formed on the dielectric material within the core of the nano-ribbon channel and on the substrate adjacent to the nano-ribbon transistor device. A metal contact is formed in the back-bias control region.

Abstract translation: 本发明的实施例包括一种用于制造纳米带状晶体管器件的方法及其结果。 一种纳米带状晶体管器件，包括衬底，纳米带通道，纳米带通道中心的芯区域，形成在纳米带通道周围的栅极，形成在栅极的每个侧壁上的隔离物，以及 提供了与每个间隔物相邻外延形成的源极和漏极区域。 选择性地蚀刻纳米带通道中心的核心区域。 介电材料沉积在纳米带通道的暴露部分上。 在纳米带通道的芯内的电介质材料上和与纳米带晶体管器件相邻的衬底上形成背偏压控制区。 在背偏压控制区域中形成金属接触。

公开(公告)号：US09472471B1

公开(公告)日：2016-10-18

申请号：US15057299

申请日：2016-03-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Sanghoon Lee ,  Alexander Reznicek

IPC: H01L21/302 ,  H01L21/84 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8258

CPC classification number: H01L21/845 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/8258 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775

Abstract: A method of CMOS construction may include stacked III-V nanowires and stacked Ge nanowires. The CMOS construction may include a hybrid orientation with surface SOI and a standard substrate.

Abstract translation: CMOS结构的方法可以包括堆叠的III-V纳米线和堆叠的Ge纳米线。 CMOS结构可以包括具有表面SOI和标准衬底的混合取向。

公开(公告)号：US09362383B1

公开(公告)日：2016-06-07

申请号：US14856811

申请日：2015-09-17

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/335 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/51 ,  H01L21/84 ,  H01L29/10

CPC classification number: H01L21/823425 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/1066 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A structure includes a substrate and a tunnel field effect transistor (TFET). The TFET includes a source region disposed in the substrate having an overlying source contact, the source region containing first semiconductor material having a first doping type; a drain region disposed in the substrate having an overlying drain contact, the drain region containing second semiconductor material having a second, opposite doping type; and a gate structure that overlies a channel region between the source and the drain. The source region and the drain region are asymmetric with respect to one another such that one contains a larger volume of semiconductor material than the other one. A method is disclosed to fabricate a plurality of the TFETs using a plurality of spaced apart mandrels having spacers. A pair of the mandrels and the associated spacers is processed to form four adjacent TFETs without requiring intervening lithographic processes.

Abstract translation: 一种结构包括衬底和隧道场效应晶体管（TFET）。 所述TFET包括设置在所述衬底中的源极区域，所述源极区域具有覆盖源极接触，所述源极区域包含具有第一掺杂类型的第一半导体材料; 漏极区域，设置在所述衬底中，具有上覆漏极接触，所述漏极区域包含具有第二相反掺杂类型的第二半导体材料; 以及覆盖在源极和漏极之间的沟道区域的栅极结构。 源极区域和漏极区域相对于彼此是不对称的，使得一个包含比另一个更大体积的半导体材料。 公开了一种使用具有间隔物的多个间隔开的心轴制造多个TFET的方法。 处理一对心轴和相关的间隔物以形成四个相邻的TFET，而不需要中间的光刻工艺。

公开(公告)号：US09034704B2

公开(公告)日：2015-05-19

申请号：US13970663

申请日：2013-08-20

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn

IPC: H01L21/8238 ,  H01L29/06 ,  H01L21/84 ,  H01L29/423 ,  H01L27/11 ,  H01L27/12 ,  H01L21/70

CPC classification number: H01L29/0673 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/775

Abstract: A memory device includes a first plurality of semiconductor nanowires tethered between landing pads and suspended over a substrate. A first gate electrode surrounds each of the first plurality of semiconductor nanowires, making them gate-all-around (GAA) semiconductor nanowires. First, second, and third field effect transistors (FETs) are formed by the first plurality of semiconductor nanowires. The memory device also includes a second plurality of semiconductor nanowires tethered between landing pads and suspended over the substrate. A second gate electrode surrounds each of the second plurality of semiconductor nanowires, making them GAA semiconductor nanowires. Fourth, fifth, and sixth FETs are formed by the second plurality of semiconductor nanowires. The first gate electrode is aligned with and cross-coupled to a landing pad of the second plurality of semiconductor nanowires, and the second gate electrode is aligned with and cross-coupled to a landing pad of the first plurality of semiconductor nanowires.

Abstract translation: 存储器件包括连接在着陆焊盘之间并悬挂在衬底上的第一多个半导体纳米线。 第一栅极电极围绕第一多个半导体纳米线中的每一个，使得它们成为栅极全绕（GAA）半导体纳米线。 第一，第二和第三场效应晶体管（FET）由第一多个半导体纳米线形成。 存储器件还包括拴在着陆焊盘之间并悬挂在衬底上的第二多个半导体纳米线。 第二栅电极围绕第二多个半导体纳米线中的每一个，使其成为GAA半导体纳米线。 第四，第五和第六FET由第二多个半导体纳米线形成。 第一栅极电极与第二多个半导体纳米线的层叠焊盘对准并交叉耦合，并且第二栅极电极与第一多个半导体纳米线的焊盘对准并交叉耦合。

公开(公告)号：US09000530B2

公开(公告)日：2015-04-07

申请号：US13868626

申请日：2013-04-23

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn

IPC: H01L21/70 ,  H01L29/06 ,  H01L27/092 ,  H01L21/84 ,  H01L29/423 ,  H01L27/11 ,  H01L27/12 ,  H01L21/8238

CPC classification number: H01L29/0673 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/775

Abstract: A memory device includes a first plurality of semiconductor nanowires tethered between landing pads and suspended over a substrate. A first gate electrode surrounds each of the first plurality of semiconductor nanowires, making them gate-all-around (GAA) semiconductor nanowires. First, second, and third field effect transistors (FETs) are formed by the first plurality of semiconductor nanowires. The memory device also includes a second plurality of semiconductor nanowires tethered between landing pads and suspended over the substrate. A second gate electrode surrounds each of the second plurality of semiconductor nanowires, making them GAA semiconductor nanowires. Fourth, fifth, and sixth FETs are formed by the second plurality of semiconductor nanowires. The first gate electrode is aligned with and cross-coupled to a landing pad of the second plurality of semiconductor nanowires, and the second gate electrode is aligned with and cross-coupled to a landing pad of the first plurality of semiconductor nanowires.

公开(公告)号：US20240127096A1

公开(公告)日：2024-04-18

申请号：US18046468

申请日：2022-10-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Martin O. Sandberg ,  Abram L. Falk ,  Karthik Balakrishnan ,  Jason S. Orcutt

IPC: G06N10/40

CPC classification number: G06N10/40

Abstract: Methods and systems for mitigating the effects of defects in a quantum processor are provided. A mitigation system includes a quantum processor having multiple qubits. The system includes an array of light emitting sources. Each light emitting source is aligned with a qubit on the quantum processor. The system includes a controller configured to receive a selection of a qubit and to enable a light emitting source from the array of light emitting sources to emit light to the selected qubit. The light is use to scramble strongly coupled two-level systems (TLSs) in the quantum processor.

公开(公告)号：US20240127095A1

公开(公告)日：2024-04-18

申请号：US18046467

申请日：2022-10-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Abram L. Falk ,  Martin O. Sandberg ,  Jason S. Orcutt

IPC: G06N10/40 ,  G02B5/20

CPC classification number: G06N10/40 ,  G02B5/201

Abstract: Methods and systems for mitigating the effects of defects in a quantum processor are provided. A mitigation system includes a quantum processor comprising a plurality of qubits. The system includes a light emitting source that can be tuned to produce light pulses of different wavelengths. The system includes an array of bandpass filters. Each bandpass filter is aligned with a qubit on the quantum processor and has a unique pass band. The system may include a controller configured to receive a selection of a qubit and to tune the light emitting source to emit a light pulse having a wavelength that falls within a range of a bandpass filter that is aligned with the selected qubit. The light pulse is used to scramble an ensemble of strongly coupled two-level system (TLS) in the processor.