公开(公告)号：US20240113223A1

公开(公告)日：2024-04-04

申请号：US18530113

申请日：2023-12-05

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Kirk D. Prall ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L29/786 ,  G11C11/409 ,  H01L29/423 ,  H01L29/66 ,  H10B12/00

CPC classification number: H01L29/78642 ,  G11C11/409 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/7869 ,  H10B12/05 ,  H10B12/30 ,  H10B12/50

Abstract: A transistor comprising threshold voltage control gates. The transistor also comprises active control gates adjacent opposing first sides of a channel region, the threshold voltage control gates adjacent opposing second sides of the channel region, and a dielectric region between the threshold voltage control gates and the channel region and between the active control gates and the channel region. A semiconductor device comprising memory cells comprising the transistor is also disclosed, as are systems comprising the memory cells, methods of forming the semiconductor device, and methods of operating a semiconductor device.

公开(公告)号：US20240099026A1

公开(公告)日：2024-03-21

申请号：US18519964

申请日：2023-11-27

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H10B63/00 ,  G11C5/12 ,  G11C13/00 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/84 ,  G11C5/12 ,  G11C13/0002 ,  H01L21/823487 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/78696 ,  H10B63/22 ,  H10B63/24 ,  H10B63/34 ,  H10N70/011 ,  H10N70/245 ,  H10N70/828 ,  H10N70/841 ,  H10N70/883 ,  G11C11/401 ,  G11C2213/79

Abstract: Semiconductor devices are disclosed. A semiconductor device may include a hybrid transistor configured in a vertical orientation. The hybrid transistor may include a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a first material and the channel material includes a second, different material.

公开(公告)号：US20240074211A1

公开(公告)日：2024-02-29

申请号：US18238291

申请日：2023-08-25

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H10B63/00 ,  G11C5/06 ,  H10B63/10 ,  H10N70/00

CPC classification number: H10B63/34 ,  G11C5/063 ,  H10B63/10 ,  H10B63/845 ,  H10N70/883

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a conductive region; a memory cell including a memory element, a first portion, a second portion, a dielectric portion, and a third portion; and a data line formed over the second and third portions of the memory cell. The memory element is formed over the conductive region. The first portion is formed over the memory element and includes a first conductive material. The second portion is formed over the first portion and includes a second conductive material. The dielectric portion includes a first side adjacent the memory element, the first portion, and the second portion. The third portion includes a third conductive material and is adjacent a second side of the dielectric portion and separated from the memory element, the first portion, and the second portion by the dielectric portion.

公开(公告)号：US11856799B2

公开(公告)日：2023-12-26

申请号：US17182953

申请日：2021-02-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L21/8234 ,  H10B63/00 ,  G11C13/00 ,  H01L27/12 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  G11C5/12 ,  H10N70/00 ,  H10N70/20 ,  G11C11/401 ,  G11C11/16 ,  G11C11/22

CPC classification number: H10B63/84 ,  G11C5/12 ,  G11C13/0002 ,  H01L21/823487 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/7869 ,  H01L29/78642 ,  H01L29/78696 ,  H10B63/22 ,  H10B63/24 ,  H10B63/34 ,  H10N70/011 ,  H10N70/245 ,  H10N70/828 ,  H10N70/841 ,  H10N70/883 ,  G11C11/1659 ,  G11C11/2259 ,  G11C11/401 ,  G11C13/003 ,  G11C2213/79 ,  H01L29/78618

Abstract: Methods of forming a semiconductor device are disclosed. A method comprising forming a hybrid transistor supported by a substrate. Forming the hybrid transistor comprises forming a source including a first low bandgap high mobility material, and forming a channel including a high bandgap low mobility material coupled with the first low bandgap high mobility material. Forming the hybrid transistor further comprises forming a drain including a second low bandgap high mobility material coupled with the a high bandgap low mobility material, and forming a gate separated from the channel via a gate oxide material. Methods of forming a transistor are also disclosed.

公开(公告)号：US11848053B2

公开(公告)日：2023-12-19

申请号：US18095025

申请日：2023-01-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vladimir Mikhalev ,  Haitao Liu

IPC: H01L29/423 ,  H01L29/66 ,  H01L27/11556 ,  G11C16/04 ,  H01L29/792 ,  H01L29/788 ,  H01L21/28 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/0483 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Transistors, and memories including such transistors, might include an active area having a first conductivity type, first and second source/drain regions in the active area and having a second conductivity type, and a plurality of control gates between the first and second source/drain regions and the second source/drain region, wherein each control gate of the plurality of control gates includes a respective first control gate portion overlying a first side of the active area, and a respective second control gate portion connected to its respective first control gate portion that is either adjacent to a second side of the active area orthogonal to the first side of the active area, or underlying a second side of the active area opposite the first side of the active area.

公开(公告)号：US11805653B2

公开(公告)日：2023-10-31

申请号：US17145131

申请日：2021-01-08

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  Akira Goda ,  Lifang Xu

IPC: H01L27/11573 ,  H10B43/40 ,  G11C16/08 ,  H01L23/532 ,  H01L21/28 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: H10B43/40 ,  G11C16/08 ,  H01L23/5329 ,  H01L29/40117 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

公开(公告)号：US11791391B1

公开(公告)日：2023-10-17

申请号：US17655479

申请日：2022-03-18

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Karthik Sarpatwari ,  Richard E. Fackenthal

IPC: H01L29/423 ,  H01L27/02 ,  H01L27/092 ,  G11C5/02 ,  H10B10/00

CPC classification number: H01L29/42372 ,  G11C5/025 ,  H01L27/0207 ,  H01L27/092 ,  H10B10/12

Abstract: An inverter includes a transistor, an additional transistor overlying the transistor, and a hybrid gate electrode interposed between and shared by the transistor and the additional transistor. The hybrid gate electrode includes a region overlying a channel structure of the transistor, an additional region overlying the region and underlying an additional channel structure of the additional transistor, and further region interposed between the region and the additional region. The region has a first material composition. The additional region has a second material composition different than the first material composition of the region. Memory devices and electronic systems are also described.

公开(公告)号：US11742380B2

公开(公告)日：2023-08-29

申请号：US17714740

申请日：2022-04-06

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Haitao Liu ,  Matthew J. King

IPC: G11C16/16 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L29/0638 ,  G11C16/0483 ,  G11C16/16 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of the topmost select gate transistors to strings of memory cells upon application of a voltage to the gates of the topmost select gate transistors. This electric field can be provided by using a dissected plug as a contact to the channel structure of the topmost select gate transistor, where the dissected plug has one or more conductive regions contacting the channel structure and one or more non-conductive regions contacting the channel structure. The dissected plug can be part of a contact between the data line and the channel structure. Additional devices, systems, and methods are discussed.

公开(公告)号：US20230269922A1

公开(公告)日：2023-08-24

申请号：US18141046

申请日：2023-04-28

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H10B12/00 ,  G11C11/401

CPC classification number: H10B12/20 ,  G11C11/401

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a substrate, a conductive plate located over the substrate to couple a ground connection, a data line located between the substrate and the conductive plate, a memory cell, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled between the data line and the conductive plate, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.

公开(公告)号：US20230207699A1

公开(公告)日：2023-06-29

申请号：US17695634

申请日：2022-03-15

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Sameer Chhajed

IPC: H01L29/786 ,  H01L27/108

CPC classification number: H01L29/78618 ,  H01L27/10808 ,  H01L29/78642

Abstract: A transistor comprises a pair of source/drain regions having a channel region there-between. A gate is adjacent the channel region with a gate insulator being between the gate and the channel region. A fixed-charge material is adjacent the source/drain regions. Insulating material is between the fixed-charge material and the source/drain regions. The insulating material and the fixed-charge material comprise different compositions relative one another. The fixed-charge material has charge density of at least 1 x 1011 charges/cm2.