公开(公告)号：US20250096202A1

公开(公告)日：2025-03-20

申请号：US18788541

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Bret K. Street ,  Akshay N. Singh ,  Kunal R. Parekh ,  Wei Zhou

IPC: H01L25/065 ,  H01L23/00 ,  H10B80/00

Abstract: A semiconductor device assembly is provided. The semiconductor device assembly includes a logic die, a first plurality of stacked memory dies electrically coupled with the logic die, and a second plurality of stacked memory dies mounted on and electrically coupled with the first plurality of stacked memory dies. A first dielectric material is disposed around the first plurality of stacked memory dies. A second dielectric material is disposed at the first dielectric material and surrounding the second plurality of stacked memory dies. A third dielectric material is disposed between the first plurality of stacked memory dies and the second plurality of stacked memory dies and between the first dielectric material and the second dielectric material.

公开(公告)号：US20250079366A1

公开(公告)日：2025-03-06

申请号：US18788588

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Akshay N. Singh ,  Kunal R. Parekh ,  Bharat Bhushan

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor device assembly with layered dielectric is disclosed. The semiconductor device assembly includes a first semiconductor die and a second semiconductor die coupled with the first semiconductor die. The second semiconductor die is at least partially surrounded by a tensile dielectric and a compressive dielectric disposed at the first semiconductor die. The tensile dielectric is configured to experience tensile stress at an upper surface and compressive stress at a lower surface (e.g., the tensile dielectric will warp concave down). In contrast, the compressive dielectric is configured to experience compressive stress at an upper surface and tensile stress at a lower surface (e.g., the compressive dielectric will warp concave up). As a result, stress in the semiconductor device assembly can be reduced and overall yield can be improved.

公开(公告)号：US12183716B2

公开(公告)日：2024-12-31

申请号：US17711583

申请日：2022-04-01

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K Street ,  Kunal R. Parekh

IPC: H01L25/00 ,  H01L25/065

Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor die and a molding material. The semiconductor die may have a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein. The molding material may be laterally adjacent to the semiconductor die.

公开(公告)号：US20240079369A1

公开(公告)日：2024-03-07

申请号：US17938917

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Bret K. Street ,  Wei Zhou ,  Kyle K. Kirby ,  Amy R. Griffin ,  Thiagarajan Raman ,  Jaekyu Song

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/48 ,  H01L24/16 ,  H01L24/32 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48011 ,  H01L2224/4809 ,  H01L2224/48145 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438

Abstract: This document discloses techniques, apparatuses, and systems for connecting semiconductor dies through traces. A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die includes a first dielectric layer at which first circuitry is disposed. The second semiconductor die includes a second dielectric layer at which second circuitry is disposed. One or more traces extend from a side surface of the first dielectric layer and at a side surface of the second dielectric layer to electrically couple the first circuitry and the second circuitry. In doing so, rigid connective structures may not be needed to couple the first semiconductor die and the second semiconductor die.

公开(公告)号：US20240071976A1

公开(公告)日：2024-02-29

申请号：US17899574

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L24/32 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/08 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0801 ,  H01L2224/08055 ,  H01L2224/08056 ,  H01L2224/16014 ,  H01L2224/16055 ,  H01L2224/16148 ,  H01L2224/27622 ,  H01L2224/29011 ,  H01L2224/29191 ,  H01L2224/32013 ,  H01L2224/32054 ,  H01L2224/32058 ,  H01L2224/3207 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/83009 ,  H01L2224/83099 ,  H01L2224/83896 ,  H01L2224/83907 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541

Abstract: This document discloses techniques, apparatuses, and systems for a semiconductor device with a polymer layer. A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die has a first active side with first circuitry and a first back side opposite the first active side. Contact pads and a layer of polymer material are disposed at the first back side such that the layer of polymer material includes openings that expose the contact pads. The second semiconductor die has second circuitry disposed at a second active side. Interconnect structures are also disposed at the second active side such that the interconnect structures extend into the openings and couple to contact pads. A passivation layer (e.g., dielectric material) is disposed at the second active side and directly bonded to the layer of polymer material to reliably couple the two semiconductor dies.

公开(公告)号：US20240063207A1

公开(公告)日：2024-02-22

申请号：US17892038

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Terrence B. McDaniel ,  Amy R. Griffin ,  Kyle K. Kirby ,  Thiagarajan Raman

IPC: H01L25/00 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H10B80/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/34 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L21/568 ,  H01L24/11 ,  H01L24/80 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H10B80/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L23/345 ,  H01L23/3135 ,  H01L2221/68381 ,  H01L2221/68368 ,  H01L2224/0557 ,  H01L2224/06134 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/05555 ,  H01L2224/05571 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2224/80006

Abstract: Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a cavity configured to entrap a gas during the formation of the bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.

公开(公告)号：US20240063094A1

公开(公告)日：2024-02-22

申请号：US17892034

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Kunal R. Parekh ,  Wei Zhou

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/13 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L25/0657 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/13 ,  H01L21/76898 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2224/73204 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L21/308

Abstract: A semiconductor device includes a semiconductor substrate including a cavity and a peripheral region surrounding the cavity. The peripheral region includes a first surface and a second surface opposite the first surface. The cavity extends from the first surface partially through the semiconductor substrate to a third surface. The third surface is parallel to the first surface and is located between the first surface and the second surface. The semiconductor device also includes a plurality of through-silicon vias (TSVs) extending between the first surface and the third surface.

公开(公告)号：US20240055400A1

公开(公告)日：2024-02-15

申请号：US17884475

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Bret K. Street ,  Kyle K. Kirby ,  Wei Zhou ,  Thiagarajan Raman

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06582

Abstract: This document discloses techniques, apparatuses, and systems for providing a semiconductor device assembly with a substrate for vertically assembled semiconductor dies. A semiconductor assembly is described that includes a semiconductor die coupled to a substrate such that an active surface of the semiconductor die is substantially orthogonal to a top surface of the substrate. The substrate includes a surface having a recessed slot at which a side surface of the semiconductor die couples. The semiconductor die includes a contact pad that couples to a contact pad at the recessed slot. In doing so, the techniques, apparatuses, and systems herein enable a robust and cost-efficient semiconductor device to be assembled.

公开(公告)号：US11894327B2

公开(公告)日：2024-02-06

申请号：US17405604

申请日：2021-08-18

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Chien Wen Huang

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L23/36

CPC classification number: H01L24/05 ,  H01L23/296 ,  H01L23/3171 ,  H01L23/36 ,  H01L24/03 ,  H01L24/06 ,  H01L2224/03019 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06519 ,  H01L2924/3511

Abstract: Semiconductor devices including one or more interfacing segments patterned within an outer protective layer and associated systems and methods are disclosed herein. The one or more interfacing segments may provide attachment interfaces/surfaces for connection pads. The one or more interfacing segments or a portion thereof may remain uncovered or exposed and provide warpage control for the corresponding semiconductor device.

公开(公告)号：US11862591B2

公开(公告)日：2024-01-02

申请号：US17411229

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L24/08 ,  H01L24/03 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/0219 ,  H01L2224/03821 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Conductive buffer layers for semiconductor die assemblies, and associated systems and methods are disclosed. In an embodiment, a semiconductor die assembly includes first and second semiconductor dies directly bonded to each other. The first semiconductor die includes a first copper pad and the second semiconductor die includes a second copper pad. The first and second copper pads form an interconnect between the first and second semiconductor dies, and the interconnect includes a conductive buffer material between the first and second copper pads, where the conductive buffer material includes aggregates of conductive particles. In some embodiments, the first and second copper pads are not conjoined but electrically connected to each other through the conductive buffer material. In some embodiments, the conductive buffer material is porous such that the aggregates of conductive particles can be compressed together in response to the pressure applied to the conductive buffer layer.