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    INTERCONNECT STRUCTURES WITH PARTIALLY SELF ALIGNED VIAS AND METHODS TO PRODUCE SAME
    83.
    发明申请
    INTERCONNECT STRUCTURES WITH PARTIALLY SELF ALIGNED VIAS AND METHODS TO PRODUCE SAME 审中-公开
    具有部分自对准VIAS的互连结构及其生产方法

    公开(公告)号：US20090200683A1

    公开(公告)日：2009-08-13

    申请号：US12030756

    申请日：2008-02-13

    申请人： Matthew Earl Colburn ,  Nicholas C. Fuller ,  Elbert Huang ,  Satyanarayana V. Nitta

    发明人： Matthew Earl Colburn ,  Nicholas C. Fuller ,  Elbert Huang ,  Satyanarayana V. Nitta

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L21/76811 ,  H01L21/76813

    摘要： An interconnect structure having partially self aligned vias with an interlayer dielectric layer on a substrate, containing at least two conducting metal lines that traverse parallel to the substrate and at least two conducting metal vias that are orthogonal to the substrate. A method of producing the self aligned vias by depositing an interlayer dielectric layer onto a substrate, depositing at least one hardmask onto the interlayer dielectric layer, lithographically forming a via pattern with elongated via features and lithographically forming a line pattern in either order, then either transferring the line patterns first into the interlayer dielectric layer forming line features or transferring the via pattern first into the interlayer dielectric layer as long as the patterns overlap to forming self aligned via features, depositing conducting metals and filling regions corresponding to the line and via features, and planarizing and removing excess metal from the line and via features.

    摘要翻译： 具有部分自对准的通孔的互连结构，其中在衬底上具有层间电介质层，其包含至少两条横穿平行于衬底的导电金属线和至少两个与衬底正交的导电金属通孔。 一种通过在衬底上沉积层间电介质层来生产自对准通孔的方法，将至少一个硬掩模沉积到层间电介质层上，以光刻方式形成具有细长通孔特征的通孔图案，并以任何顺序光刻形成线图案，然后 只要图案重叠以形成自对准的通孔特征，沉积导电金属和对应于该线的通孔特征的填充区域，首先将线图案首先转移到层间介质层形成线的特征中或者将该通孔图案转移到层间电介质层中 并且从线和通孔特征平坦化和去除多余的金属。

    Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity
    85.
    发明授权
    Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity 失效
    双镶嵌工艺流程可实现极少的ULK膜修饰和增强的堆叠完整性

    公开(公告)号：US07435676B2

    公开(公告)日：2008-10-14

    申请号：US11328981

    申请日：2006-01-10

    申请人： Timothy J. Dalton ,  Nicholas C. Fuller ,  Satyanarayana V. Nitta

    发明人： Timothy J. Dalton ,  Nicholas C. Fuller ,  Satyanarayana V. Nitta

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76801 ,  H01L21/76808 ,  H01L21/76829

    摘要： Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed because of the use of a sacrificial polymeric material deposited onto the dielectric and optional organic adhesion promoter during the barrier open step done prior to ashing the patterning material. This sacrificial film protects the dielectric and optional organic adhesion promoter from modification/consumption during the subsequent ashing step during which the polymeric film is removed.

    摘要翻译： 本文提供了具有最小化学计量变化的有机硅酸盐玻璃层间介电材料和任选的用于半导体器件的完整有机粘合促进剂的互连结构。 互连结构能够提供改进的器件性能，功能性和可靠性，因为与常规使用的那些相比，堆叠的有效介电常数降低，因为使用沉积在电介质上的牺牲聚合物材料和任选的有机粘合促进剂 在灰化图案材料之前完成的阻挡层开口步骤。 该牺牲膜在后续的灰化步骤期间保护电介质和任选的有机粘合促进剂免于修饰/消耗，在此期间除去聚合物膜。

    Interconnects containing first and second porous low-k dielectrics separated by a porous buried etch stop layer
    86.
    发明授权
    Interconnects containing first and second porous low-k dielectrics separated by a porous buried etch stop layer 有权
    互连件包含由多孔掩埋蚀刻停止层隔开的第一和第二多孔低k电介质

    公开(公告)号：US06831366B2

    公开(公告)日：2004-12-14

    申请号：US10396274

    申请日：2003-03-25

    申请人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    发明人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    IPC分类号： H01L2352

    CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.

    摘要翻译： 提供了其中不存在微沟槽的低k电介质金属导体互连结构以及形成这种结构的方法。 具体地说，上述结构是通过提供一种互连结构来实现的，所述互连结构至少包括多层电介质材料，所述多层电介质材料依次应用于单个旋涂工具中，然后在单个步骤中固化，并且多个图案化的金属导体在多层纺丝 - 电介质。 使用具有位于具有第一原子组成的多孔低k电介质的线路和通孔电介质层之间的第二原子组成的掩埋蚀刻停止层来获得对导体电阻的控制。 本发明的互连结构还包括有助于形成双镶嵌型互连结构的硬掩模。 选择第一和第二组合物以获得至少10至1或更高的蚀刻选择性，并且选自具有特定原子组成和其它可发现量的多孔低k有机或无机材料的特定组。

    Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials
    89.
    发明授权
    Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials 有权
    混合低k互连结构由2个旋涂电介质材料组成

    公开(公告)号：US06677680B2

    公开(公告)日：2004-01-13

    申请号：US09795429

    申请日：2001-02-28

    申请人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    发明人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    IPC分类号： H01L2348

    CPC分类号： H01L21/76835 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/76811

    摘要： A metal wiring plus low-k dielectric interconnect structure of the dual damascene-type is provided wherein the conductive metal lines and vias are built into a hybrid low-k dielectric which includes two spun-on dielectrics that have different atomic compositions and at least one of the two spun-on dielectrics is porous. The two spun-on dielectrics used in forming the inventive hybrid low-k dielectric each have a dielectric constant of about 2.6 or less, preferably each dielectric of the hybrid structure has a k of from about 1.2 to about 2.2. By utilizing the inventive hybrid low-k dielectric excellent control over metal line resistance (trench depth) is obtained, without no added cost. This is achieved without the use of a buried etch stop layer, which if present, would be formed between the two spun-on dielectrics. Moreover, the spun-on dielectrics of the hybrid low-k dielectric have distinctly different atomic compositions enabling control over the conductor resistance using the bottom spun-on dielectric (i.e., via dielectric) as an inherent etch stop layer for the upper spun-on dielectric (i.e., line dielectric).

    摘要翻译： 提供了一种双镶嵌型金属布线加上低k电介质互连结构，其中导电金属线和通孔内置于混合低k电介质中，该电介质包括两个具有不同原子组成的旋转电介质和至少一个 的两个旋转电介质是多孔的。 用于形成本发明的混合低k电介质的两个旋转电介质各自具有约2.6或更小的介电常数，优选混合结构的每个电介质具有约1.2至约2.2的k。 通过利用本发明的混合低k电介质，获得对金属线电阻（沟槽深度）的优异控制，而不增加成本。 这是在没有使用掩埋蚀刻停止层的情况下实现的，如果存在的话，它将在两个旋转电介质之间形成。 此外，混合低k电介质的旋转电介质具有明显不同的原子组成，使得能够使用底部纺丝电介质（即，通过电介质）控制导体电阻，作为用于上纺丝的固有蚀刻停止层 电介质（即线电介质）。