利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

253 条记录 (耗时 0.036 秒)

    Transistor having replacement metal gate and process for fabricating the same
    82.
    发明申请
    Transistor having replacement metal gate and process for fabricating the same 有权
    具有替代金属栅极的晶体管及其制造方法

    公开(公告)号：US20120061772A1

    公开(公告)日：2012-03-15

    申请号：US12880085

    申请日：2010-09-11

    申请人： Dechao Guo ,  Keith Kwong Hon Wong

    发明人： Dechao Guo ,  Keith Kwong Hon Wong

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L21/28079 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42372 ,  H01L29/517 ,  H01L29/66545

    摘要： A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor.

    摘要翻译： 通过在衬底的掺杂区域上去除多晶硅栅极并在衬底上形成掩模层来制造晶体管，使得掺杂区域通过掩模层内的孔露出。 界面层沉积在掩模层的顶表面和侧表面上以及在掺杂区的顶表面上。 适于降低晶体管的阈值电压和/或降低晶体管的反型层的厚度的层被沉积在界面层上。 该层包括扩散到界面层中的金属，例如铝或镧，并且还包括氧化物，例如氧化铪。 在掩模层的孔内形成导电塞，例如金属塞。 界面层，界面层上的层和导电插塞是晶体管的替代栅极。

    Structure for metal cap applications
    83.
    发明授权
    Structure for metal cap applications 有权
    金属盖应用结构

    公开(公告)号：US08133810B2

    公开(公告)日：2012-03-13

    申请号：US12881806

    申请日：2010-09-14

    申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Haining Yang

    发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Haining Yang

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76885 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849

    摘要： An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.

    摘要翻译： 提供了一种互连结构，其中嵌入电介质材料内的导电特征被金属覆盖层封盖，但在最终结构中绝缘材料表面上没有金属残留物。 与现有技术的互连结构相比，本发明的互连结构具有改善的介电击穿强度。 此外，本发明的互连结构对于半导体工业具有更好的可靠性和技术可扩展性。 本发明的互连结构包括具有嵌入其中的至少一个金属封盖的导电特征的电介质材料，其中所述至少一个金属封端的导电特征的顶部在电介质材料的上表面上方延伸。 电介质覆盖层位于电介质材料上，并且封装在电介质材料的上表面上方延伸的所述至少一个金属封盖导电特征的顶部。

    ADAPTIVE CHUCK FOR PLANAR BONDING BETWEEN SUBSTRATES
    84.
    发明申请
    ADAPTIVE CHUCK FOR PLANAR BONDING BETWEEN SUBSTRATES 失效
    用于基板之间的平面结合的自适应块

    公开(公告)号：US20110083786A1

    公开(公告)日：2011-04-14

    申请号：US12575968

    申请日：2009-10-08

    申请人： Dechao Guo ,  Fei Liu ,  Leathen Shi ,  Keith Kwong Hon Wong

    发明人： Dechao Guo ,  Fei Liu ,  Leathen Shi ,  Keith Kwong Hon Wong

    IPC分类号： B29C65/78 ,  H01L21/683

    CPC分类号： H01L21/6833 ,  B32B37/0007 ,  B32B2457/14 ,  Y10T156/1002

    摘要： An electrostatic chuck includes an array of independently biased conductive chuck elements, an array of sensor-conductor assemblies, and/or a combination of an array of sensor-conductor assemblies and at least one motorized chuck. Conductive chuck elements, either standing alone or embedded in a sensor-conductor assembly, are independently biased electrostatically to compensate for bowing and/or warping of a substrate thereupon so that the substrate can be bonded with a planar surface. A single electrostatic chuck can be employed to reduce the bowing and warping of one of the two substrates to be bonded, or two electrostatic chucks can be employed to minimize the bowing and warping of two substrates to be bonded.

    摘要翻译： 静电卡盘包括独立偏置的导电卡盘元件的阵列，传感器 - 导体组件的阵列，和/或传感器 - 导体组件阵列和至少一个电动卡盘的组合。 独立地或嵌入传感器 - 导体组件中的导电卡盘元件被静电地独立地偏置以补偿其上的衬底的弯曲和/或翘曲，使得衬底可以与平坦表面结合。 可以使用单个静电卡盘来减少要接合的两个基板中的一个的弯曲和翘曲，或者可以使用两个静电卡盘来最小化要接合的两个基板的弯曲和翘曲。

    METAL GATE AND HIGH-K DIELECTRIC DEVICES WITH PFET CHANNEL SiGe
    85.
    发明申请
    METAL GATE AND HIGH-K DIELECTRIC DEVICES WITH PFET CHANNEL SiGe 有权
    具有PFET通道SiGe的金属栅极和高K介质器件

    公开(公告)号：US20110068369A1

    公开(公告)日：2011-03-24

    申请号：US12563032

    申请日：2009-09-18

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L21/823857

    摘要： A method for fabricating a circuit structure is disclosed. The method includes depositing epitaxially a SiGe layer onto both NFET and PFET portions of a Si surface. Blanket disposing a first sequence of layers over the SiGe layer, including a high-k dielectric and a metal, and incorporating this first sequence of layers into the gatestacks and gate insulators of both NFET devices and PFET devices. This first sequence of layers is selected to yield desired device parameter values for the PFET devices. The method further includes removing the gatestack, the gate dielectric, and the SiGe layer, and re-forming the NFET devices by deploying a second sequence of layers that include a second high-k dielectric and a second metal. The second sequence of layers is selected to yield desired device parameter values for the NFET devices. A circuit structure is also disclosed. PFET devices have a gate dielectric with a high-k dielectric, a gatestack with a metal, and a silicide formed over the p-source/drain. NFET devices also include a gate dielectric with a high-k dielectric, a gatestack with a metal, and silicide formed over the n-source/drain. An epitaxial SiGe layer over the substrate surface is present everywhere in the device structures with the exception that it is absent underneath the NFET gate dielectric. The PFET and NFET device parameters are independently optimized through the composition of their gate dielectrics and gate stacks.

    摘要翻译： 公开了一种制造电路结构的方法。 该方法包括将SiGe层外延沉积到Si表面的NFET和PFET部分上。 毯子在SiGe层上设置第一层次序列，包括高k电介质和金属，并将该第一层序列并入到两个NFET器件和PFET器件的绝缘体和栅极绝缘体中。 选择该第一层次序列以产生PFET器件的期望的器件参数值。 该方法还包括去除盖板，栅极电介质和SiGe层，以及通过布置包括第二高k电介质和第二金属的第二层序列来重新形成NFET器件。 选择第二层次序列以产生NFET器件的期望的器件参数值。 还公开了电路结构。 PFET器件具有具有高k电介质的栅极电介质，具有金属的栅极电极和形成在p源极/漏极上的硅化物。 NFET器件还包括具有高k电介质的栅极电介质，具有金属的Gatestack以及形成在n源极/漏极上的硅化物。 在衬底表面上的外延SiGe层存在于器件结构中的任何地方，不同的是它不在NFET栅极电介质的下方。 PFET和NFET器件参数通过其栅极电介质和栅极叠层的组成独立优化。

    CONFORMAL ADHESION PROMOTER LINER FOR METAL INTERCONNECTS
    87.
    发明申请
    CONFORMAL ADHESION PROMOTER LINER FOR METAL INTERCONNECTS 失效
    用于金属互连的一致粘合促进剂衬里

    公开(公告)号：US20100038789A1

    公开(公告)日：2010-02-18

    申请号：US12190906

    申请日：2008-08-13

    申请人： Tien-Jen Cheng ,  Zhengwen Li ,  Keith Kwong Hon Wong ,  Huilong Zhu

    发明人： Tien-Jen Cheng ,  Zhengwen Li ,  Keith Kwong Hon Wong ,  Huilong Zhu

    IPC分类号： H01L21/768 ,  H01L23/532

    CPC分类号： H01L23/53238 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76868 ,  H01L21/76877 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A dielectric layer is patterned with at least one line trough and/or at least one via cavity. A metallic nitride liner is formed on the surfaces of the patterned dielectric layer. A metal liner is formed on the surface of the metallic nitride liner. A conformal copper nitride layer is formed directly on the metal liner by atomic layer deposition (ALD) or chemical vapor deposition (CVD). A Cu seed layer is formed directly on the conformal copper nitride layer. The at least one line trough and/or the at least one via cavity are filled with an electroplated material. The direct contact between the conformal copper nitride layer and the Cu seed layer provides enhanced adhesion strength. The conformal copper nitride layer may be annealed to covert an exposed outer portion into a contiguous Cu layer, which may be employed to reduce the thickness of the Cu seed layer.

    摘要翻译： 用至少一个线槽和/或至少一个通孔腔对电介质层进行构图。 金属氮化物衬垫形成在图案化电介质层的表面上。 在金属氮化物衬垫的表面上形成金属衬垫。 通过原子层沉积（ALD）或化学气相沉积（CVD）直接在金属衬垫上形成共形的氮化铜层。 在适形的氮化铜层上直接形成Cu籽晶层。 至少一个线槽和/或至少一个通孔腔被电镀材料填充。 保形氮化铜层和Cu籽晶层之间的直接接触提供了增强的粘合强度。 可以将共形的氮化铜层退火以将暴露的外部部分翻转成连续的Cu层，其可用于减小Cu籽晶层的厚度。

    METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION
    88.
    发明申请
    METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION 有权
    用于高密度等离子体化学蒸气沉积的方法和装置

    公开(公告)号：US20100029082A1

    公开(公告)日：2010-02-04

    申请号：US12185339

    申请日：2008-08-04

    申请人： Daewon Yang ,  Kangguo Cheng ,  Pavel Smetana ,  Richard S. Wise ,  Keith Kwong Hon Wong

    发明人： Daewon Yang ,  Kangguo Cheng ,  Pavel Smetana ,  Richard S. Wise ,  Keith Kwong Hon Wong

    IPC分类号： H01L21/311 ,  C23C16/00

    CPC分类号： C23C16/507 ,  C23C16/345 ,  C23C16/402 ,  C23C16/45578 ,  C23C16/4586 ,  C23C16/56 ,  H01J37/20 ,  H01J37/321 ,  H01J2237/20207 ,  H01J2237/3323 ,  H01L21/31608 ,  H01L21/3185 ,  H01L27/10867

    摘要： Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.

    摘要翻译： 通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。 第二极性可以与第一极性相反。 额外的植入物可以减少第二细胞中的ESR。