公开(公告)号：US20180374549A1

公开(公告)日：2018-12-27

申请号：US15633377

申请日：2017-06-26

申请人： Micron Technology, Inc.

发明人： Renato C. Padilla ,  Jung Sheng Hoei ,  Michael G. Miller ,  Roland J. Awusie ,  Sampath K. Ratnam ,  Kishore Kumar Muchherla ,  Gary F. Besinga ,  Ashutosh Malshe ,  Harish R. Singidi

IPC分类号： G11C16/34

CPC分类号： G11C16/3427 ,  G11C11/5642 ,  G11C16/3422 ,  G11C16/3431

摘要： A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.

公开(公告)号：US20180341605A1

公开(公告)日：2018-11-29

申请号：US16054189

申请日：2018-08-03

申请人： Micron Technology, Inc.

发明人： Preston A. Thomson ,  Kishore K. Muchherla ,  Sampath K. Ratnam

IPC分类号： G06F13/24 ,  G11C16/04

CPC分类号： G06F13/24 ,  G06F11/1405 ,  G11C16/0483 ,  G11C16/102

摘要： The present disclosure is related to programming interruption management. An apparatus can be configured to detect an interruption during a programming operation and modify the programming operation to program a portion of the memory array to an uncorrectable state in response to detecting the interruption.

公开(公告)号：US10042789B2

公开(公告)日：2018-08-07

申请号：US14662280

申请日：2015-03-19

申请人： Micron Technology, Inc.

发明人： Preston A. Thomson ,  Kishore K. Muchherla ,  Sampath K. Ratnam

IPC分类号： G06F13/00 ,  G06F13/24 ,  G11C16/04 ,  G11C16/10 ,  G06F11/14

摘要： The present disclosure is related to programming interruption management. An apparatus can be configured to detect an interruption during a programming operation and modify the programming operation to program a portion of the memory array to an uncorrectable state in response to detecting the interruption.

公开(公告)号：US20180081543A1

公开(公告)日：2018-03-22

申请号：US15269518

申请日：2016-09-19

申请人： Micron Technology, Inc.

发明人： Kishore K. Muchherla ,  Ashutosh Malshe ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Christopher S. Hale ,  Renato C. Padilla

IPC分类号： G06F3/06 ,  G06F12/0893

CPC分类号： G06F3/0604 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/34 ,  G06F12/0246 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/222 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/7205 ,  G06F2212/7206

摘要： A memory device having a memory controller is configured to operate a hybrid cache including a dynamic cache including XLC blocks and a static cache including the SLC blocks. The memory controller is configured to disable at least one of the static cache or the dynamic cache. A method of operating a memory device includes partitioning a memory array into a first portion of SLC blocks and a second portion of XLC blocks, storing at least a portion of host data into the first portion of SLC blocks as a static cache; and storing at least another portion of the host data into the second portion of XLC blocks in an SLC mode as a dynamic cache responsive to a burst of host data being determined to be greater than the static cache can handle. Additional memory devices, methods, and computer systems are also described.

公开(公告)号：US09921898B1

公开(公告)日：2018-03-20

申请号：US15390833

申请日：2016-12-27

申请人： MICRON TECHNOLOGY, INC.

发明人： Michael G. Miller ,  Ashutosh Malshe ,  Violante Moschiano ,  Peter Feeley ,  Gary F. Besinga ,  Sampath K. Ratnam ,  Walter Di-Francesco ,  Renato C. Padilla, Jr. ,  Yun Li ,  Kishore Kumar Muchherla

IPC分类号： G11C16/04 ,  G06F11/07 ,  G06F3/06

CPC分类号： G06F11/073 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079

摘要： Apparatus and methods of operating such apparatus include iteratively programming a group of memory cells to respective desired data states, wherein a particular memory cell is configured to store overhead data and a different memory cell is configured to store user data; determining whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, changing the desired data state of the particular memory cell before continuing with the programming. Apparatus and methods of operating such apparatus further include reading a data state of a particular memory cell of a last written page of memory cells, and marking the page as affected by power loss during a programming operation if the particular memory cell has any data state other than a particular data state.

公开(公告)号：US20170242747A1

公开(公告)日：2017-08-24

申请号：US15046666

申请日：2016-02-18

申请人： Micron Technology, Inc.

发明人： Deping He ,  Sampath K. Ratnam

IPC分类号： G06F11/10 ,  H03M13/11 ,  H03M13/15 ,  G11C29/52

CPC分类号： G06F11/1068 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1102 ,  H03M13/13 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/29 ,  H03M13/2936 ,  H03M13/2966 ,  H03M13/356 ,  H03M13/6356 ,  H04L1/0057 ,  H04L1/0066 ,  H04L1/007 ,  H04L2001/0098

摘要： The present disclosure includes apparatuses and methods for error rate reduction. One example method comprises adding an amount of error rate reduction (ERR) data to an amount of received user data, and writing the amount of user data along with the amount of ERR data to a memory.

公开(公告)号：US20160364337A1

公开(公告)日：2016-12-15

申请号：US14735498

申请日：2015-06-10

申请人： Micron Technology, Inc.

发明人： Christopher S. Hale ,  Sampath K. Ratnam ,  Kishore K. Muchherla

IPC分类号： G06F12/08 ,  G06F3/06

CPC分类号： G06F12/0897 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0673 ,  G06F12/0238 ,  G06F12/0804 ,  G06F12/0871 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1036 ,  G06F2212/1041 ,  G06F2212/2515 ,  G06F2212/281 ,  G06F2212/6012 ,  G06F2212/608 ,  G06F2212/7203 ,  G06F2212/7206

摘要： The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.

摘要翻译： 本公开包括具有静态高速缓存和动态高速缓存的存储器。 多个实施例包括存储器，其中存储器包括被配置为作为静态单级单元（SLC）高速缓存进行操作的第一部分和被配置为当存储器的整个第一部分具有数据时被配置为作为动态SLC高速缓存操作的第二部分 存储在其中。

公开(公告)号：US09431121B2

公开(公告)日：2016-08-30

申请号：US14686100

申请日：2015-04-14

申请人： Micron Technology, Inc.

发明人： Kishore K. Muchherla ,  Sampath K. Ratnam ,  Asheesh Kwatra

IPC分类号： G11C16/26 ,  G11C16/10 ,  G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  G11C2211/5621

摘要： The present disclosure includes apparatuses and methods related to adjusting read voltages of charge-trapping flash memory. An example embodiment apparatus can include a memory array and a controller coupled to the memory array. The controller is configured to adjust a read voltage used to access a portion of the memory array based on a length of time since a last WRITE operation to the portion.

摘要翻译： 本公开包括与调整电荷捕获闪存的读取电压相关的装置和方法。 示例性实施例装置可以包括存储器阵列和耦合到存储器阵列的控制器。 控制器被配置为基于自上一次写入操作到该部分的时间长度来调整用于访问存储器阵列的一部分的读取电压。

公开(公告)号：US20150170751A1

公开(公告)日：2015-06-18

申请号：US14106070

申请日：2013-12-13

申请人： Micron Technology, Inc.

发明人： Satish K. Yanamanamanda ,  Sampath K. Ratnam

IPC分类号： G11C16/26

CPC分类号： G11C16/26 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C16/3418

摘要： The present disclosure is related to an adjusted read for a partially programmed block. A number of methods can include receiving a read request including a logical address, translating the logical address to a physical address and simultaneously determining whether a physical address associated with the read request is in a block that is partially programmed, and in response to the physical address being in the block that is partially programmed, adjusting a read signal level based on a proximity of the physical address to a last written page in the block.

摘要翻译： 本公开涉及用于部分编程块的经调整的读取。 许多方法可以包括接收包括逻辑地址的读取请求，将逻辑地址转换为物理地址并且同时确定与读取请求相关联的物理地址是否在被部分编程的块中，并且响应于物理地址 地址位于被部分编程的块中，基于物理地址与块中的最后写入页面的接近度来调整读取信号电平。

公开(公告)号：US20240296092A1

公开(公告)日：2024-09-05

申请号：US18655091

申请日：2024-05-03

申请人： MICRON TECHNOLOGY, INC.

发明人： Vamsi Pavan Rayaprolu ,  Dung Viet Nguyen ,  Zixiang Loh ,  Sampath K. Ratnam ,  Patrick R. Khayat ,  Thomas Herbert Lentz

IPC分类号： G06F11/10

CPC分类号： G06F11/1044

摘要： A request to access data programmed to a memory sub-system is received. A determination is made of whether a memory device that stores the data referenced by the request satisfies a weak memory device criterion in view of a quality rating for the device. In response to a determination that the memory device satisfies the weak memory device criterion, an error correction operation to access the data is performed in accordance with the request.