公开(公告)号：US09323711B2

公开(公告)日：2016-04-26

申请号：US14682926

申请日：2015-04-09

Applicant: Rambus Inc.

Inventor： Mark A. Horowitz ,  Craig E. Hampel ,  Alfredo Moncayo ,  Kevin S. Donnelly ,  Jared L. Zerbe

IPC: G06F13/42 ,  G06F13/40 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  H03K19/003 ,  H03K19/0185 ,  G11C19/00 ,  G06F13/10 ,  G06F3/06 ,  G06F13/16 ,  G06F13/364 ,  G06F12/10 ,  G11C16/32 ,  G06F12/02 ,  G11C7/22

CPC classification number: G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

Abstract: An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

Abstract translation: 集成电路装置包括具有输出驱动器的发送器电路。 集成电路装置包括第一寄存器，用于存储表示与发送器电路相关联的驱动强度设置的值，使得输出驱动器根据驱动强度设置输出数据。 集成电路装置还包括第二寄存器，用于存储代表与发送器电路相关联的均衡设置的值，使得输出驱动器根据均衡设置输出数据。 集成电路装置还包括第三寄存器，用于存储表示与发送器电路相关联的转换速率设置的值，使得输出驱动器根据转换速率设置输出数据。

公开(公告)号：US20160056948A1

公开(公告)日：2016-02-25

申请号：US14932192

申请日：2015-11-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L7/00

CPC classification number: H04L7/0016 ,  G11C7/04 ,  G11C2207/2254 ,  H04L7/0087 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/0292 ,  H04L25/12

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

公开(公告)号：US09257151B2

公开(公告)日：2016-02-09

申请号：US14306304

申请日：2014-06-17

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Donald C. Stark ,  Frederick A. Ware ,  Ely K. Tsern ,  Craig E. Hampel

IPC: G06F12/00 ,  G11C5/04 ,  G06F12/06 ,  G06F12/04 ,  G06F13/16 ,  G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4097 ,  H05K1/14 ,  G11C8/06 ,  H05K1/11

CPC classification number: G06F13/1678 ,  G06F12/04 ,  G06F12/06 ,  G06F12/0646 ,  G06F13/1657 ,  G06F13/4022 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1087 ,  G11C8/06 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/105 ,  G11C2207/108 ,  H05K1/117 ,  H05K1/14 ,  H05K2201/09954 ,  H05K2201/10189 ,  Y02D10/14

Abstract: Described is a printed-circuit board (PCB) that supports memory systems in which the memory core organization changes with device width. The PCB includes a memory-controller mounting location and module connectors to receive respective memory modules. Each module connector connects directly to the controller mounting location via a respective set of system data lines that does not connect to any other module connector. System data lines also extend directly between module connectors to support memory configurations with different numbers of modules. The memory systems support one memory module of a wide data width or multiple memory modules of narrower data widths. The number of physical memory banks accessed reduces with device data width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.

Abstract translation: 描述了支持存储器系统的印刷电路板（PCB），其中存储器核心组织随设备宽度而变化。 PCB包括存储器控制器安装位置和模块连接器以接收相应的存储器模块。 每个模块连接器通过不连接到任何其他模块连接器的相应的一组系统数据线直接连接到控制器安装位置。 系统数据线也直接在模块连接器之间扩展，以支持具有不同数量模块的存储器配置。 存储器系统支持宽数据宽度的一个存储器模块或较窄数据宽度的多个存储器模块。 访问的物理存储器组的数量随设备数据宽度而减少，导致相对较窄的存储器配置的功率消耗减少。 增加用于窄内存宽度的逻辑内存库的数量可以减少存储体冲突的可能性，从而提高速度性能。

公开(公告)号：US09160466B2

公开(公告)日：2015-10-13

申请号：US14535006

申请日：2014-11-06

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware ,  Richard E. Perego

IPC: H04B17/00 ,  H04B3/46 ,  H04L7/00 ,  H04L7/04 ,  H04L7/10 ,  H04L27/00 ,  H04Q1/20

CPC classification number: H04B17/11 ,  H04B17/00 ,  H04B17/21 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0087 ,  H04L7/043 ,  H04L7/10 ,  H04L27/00

Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

Abstract translation: 提供执行第一校准序列的方法和系统，例如在系统初始化时，建立操作值，其利用旨在穷举的算法，并且不时地执行第二校准序列以测量 在参数中漂移，并根据测量的漂移更新操作值。 与第一校准序列相比，第二校准序列使用较少的通信信道资源。 在一个实施例中，用于操作值的测量和收敛的第一校准序列利用长校准模式，例如大于30字节的代码，或长度为2N-1位的伪随机比特序列，其中N等于或大于 而第二校准序列使用短校准模式，例如小于16字节的固定代码，例如短至2字节长。

公开(公告)号：US09110828B2

公开(公告)日：2015-08-18

申请号：US14321718

申请日：2014-07-01

Applicant: Rambus Inc.

Inventor： Mark A. Horowitz ,  Craig E. Hampel ,  Alfredo Moncayo ,  Kevin S. Donnelly ,  Jared L. Zerbe

IPC: G06F13/10 ,  G06F13/40 ,  G06F13/42 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  H03K19/003 ,  H03K19/0185 ,  G11C19/00 ,  G11C7/22

CPC classification number: G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

Abstract: An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

Abstract translation: 集成电路装置包括具有输出驱动器的发送器电路。 集成电路装置包括第一寄存器，用于存储表示与发送器电路相关联的驱动强度设置的值，使得输出驱动器根据驱动强度设置输出数据。 集成电路装置还包括第二寄存器，用于存储代表与发送器电路相关联的均衡设置的值，使得输出驱动器根据均衡设置输出数据。 集成电路装置还包括第三寄存器，用于存储表示与发送器电路相关联的转换速率设置的值，使得输出驱动器根据转换速率设置输出数据。

公开(公告)号：US20150063433A1

公开(公告)日：2015-03-05

申请号：US14535006

申请日：2014-11-06

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware ,  Richard E. Perego

IPC: H04B17/00

CPC classification number: H04B17/11 ,  H04B17/00 ,  H04B17/21 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0087 ,  H04L7/043 ,  H04L7/10 ,  H04L27/00

Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

公开(公告)号：US08929424B2

公开(公告)日：2015-01-06

申请号：US14145966

申请日：2014-01-01

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware ,  Richard E. Perego

IPC: H04B3/46 ,  H04B17/00 ,  H04L7/00 ,  H04L7/04 ,  H04L27/00 ,  H04L7/10 ,  H04Q1/20

CPC classification number: H04B17/11 ,  H04B17/00 ,  H04B17/21 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0087 ,  H04L7/043 ,  H04L7/10 ,  H04L27/00

Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

公开(公告)号：US20140192940A1

公开(公告)日：2014-07-10

申请号：US14201778

申请日：2014-03-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L7/00

CPC classification number: H04L7/0016 ,  G11C7/04 ,  G11C2207/2254 ,  H04L7/0087 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/0292 ,  H04L25/12

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Abstract translation: 方法和系统提供在通信信道的正常操作期间不时地执行校准周期。 校准周期包括将来自发射机的正常数据源解耦，并在其位置提供校准模式。 使用第二组件上的接收器从通信链路接收校准模式。 响应于所接收的校准模式来确定通信信道的参数的校准值。 校准周期中涉及的步骤可以重新排序以考虑通信信道的利用模式。 对于双向链路，执行校准周期，其包括将接收到的校准模式存储在第二组件上的步骤，以及将这些校准模式重新发送回第一组件以用于调整第一组件上的通道的参数。

公开(公告)号：US20140189466A1

公开(公告)日：2014-07-03

申请号：US14200665

申请日：2014-03-07

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/16

CPC classification number: G06F11/1004 ,  G06F11/0703 ,  G06F11/073 ,  G06F11/1679 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation

Abstract translation: 提供了用于检测和校正存储器系统中的地址错误的系统和方法。 在存储器系统中，存储器件基于通过地址总线发送的地址生成错误检测码，并将错误检测码发送到存储器控制器。 存储器控制器响应于错误检测码向存储器件发送错误指示。 错误指示使存储器件移除接收的地址并防止存储器操作

公开(公告)号：US20130305079A1

公开(公告)日：2013-11-14

申请号：US13923656

申请日：2013-06-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

IPC: G06F1/10

CPC classification number: G11C11/4076 ,  G06F1/06 ,  G06F1/105 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1684 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4086 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

Abstract: A memory component has a signaling interface, data input/output (I/O) circuitry and command/address (CA) circuitry. The signaling interface includes an on-die terminated data I/O and an unterminated CA input. The data I/O circuitry is dedicated to sampling write data bits at the data I/O timed by a strobe signal and to transmitting read data bits timed by a first clock signal, each of the write and read data bits being valid for a bit time at the data I/O. The CA circuitry samples CA signals at the CA input in response to both rising-edge and falling-edge transitions of a second clock signal, the CA signals indicating read and write operations to be performed within the memory component.

Abstract translation: 存储器组件具有信令接口，数据输入/输出（I / O）电路和命令/地址（CA）电路。 信令接口包括片上终端数据I / O和未终止的CA输入。 数据I / O电路专用于以由选通信号定时的数据I / O对写入数据位进行采样，并发送由第一时钟信号定时的读取数据位，每个写入和读取数据位对于位有效 时间在数据I / O。 CA电路响应于第二时钟信号的上升沿和下降沿转换在CA输入端采样CA信号，CA信号指示要在存储器组件内执行的读和写操作。