公开(公告)号：US10083753B2

公开(公告)日：2018-09-25

申请号：US15842476

申请日：2017-12-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C14/00 ,  G11C29/00 ,  G11C16/26 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C14/0018 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/76 ,  G11C29/785 ,  G11C29/789 ,  G11C29/82 ,  G11C29/84 ,  G11C29/846

Abstract: A non-volatile memory is erasable by page and equipped with a row redundancy mechanism. In the case of the detection of a defective row of the memory plane, the storing of the address of the row in a non-volatile register is carried out and a redundant row having a new address is assigned. In the case of an attempt to write to the defective row, a write to the redundant row is carried out. When writing to the redundant row, the new content of the redundant row is loaded into a volatile memory and, following an operation for writing to any other row of the memory plane, a re-loading of the new content of the redundant row into the volatile memory.

公开(公告)号：US09997213B2

公开(公告)日：2018-06-12

申请号：US15657408

申请日：2017-07-24

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C7/00 ,  G11C7/06 ,  G11C8/10 ,  G11C5/14

CPC classification number: G11C7/065 ,  G11C5/14 ,  G11C7/08 ,  G11C8/10

Abstract: A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.

公开(公告)号：US20180108413A1

公开(公告)日：2018-04-19

申请号：US15842476

申请日：2017-12-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C14/00 ,  G11C29/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/16

CPC classification number: G11C14/0018 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/76 ,  G11C29/785 ,  G11C29/789 ,  G11C29/82 ,  G11C29/84 ,  G11C29/846

Abstract: A non-volatile memory is erasable by page and equipped with a row redundancy mechanism. In the case of the detection of a defective row of the memory plane, the storing of the address of the row in a non-volatile register is carried out and a redundant row having a new address is assigned. In the case of an attempt to write to the defective row, a write to the redundant row is carried out. When writing to the redundant row, the new content of the redundant row is loaded into a volatile memory and, following an operation for writing to any other row of the memory plane, a re-loading of the new content of the redundant row into the volatile memory.

公开(公告)号：US09876122B2

公开(公告)日：2018-01-23

申请号：US15365768

申请日：2016-11-30

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L29/788 ,  G11C16/04 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11553 ,  G11C16/14 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3213 ,  H01L27/11524 ,  H01L27/11521 ,  H01L27/11556

CPC classification number: H01L29/7883 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/788

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

公开(公告)号：US20170323670A1

公开(公告)日：2017-11-09

申请号：US15657408

申请日：2017-07-24

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C7/06 ,  G11C8/10 ,  G11C5/14

CPC classification number: G11C7/065 ,  G11C5/14 ,  G11C7/08 ,  G11C8/10

Abstract: A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.

公开(公告)号：US20170254848A1

公开(公告)日：2017-09-07

申请号：US15604145

申请日：2017-05-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G01R31/28 ,  G06F21/75 ,  G06F21/77 ,  G11C11/417 ,  G01R31/40 ,  G11C5/06 ,  G06F21/55 ,  G11C11/412

Abstract: A device for detecting a fault attack, including: a circuit for detecting an interruption of a power supply; a circuit for comparing the duration of the interruption with a first threshold; and a counter of the number of successive interruptions of the power supply having a duration which does not exceed the first threshold.

公开(公告)号：US20170162264A1

公开(公告)日：2017-06-08

申请号：US15140856

申请日：2016-04-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C14/00 ,  G11C16/26 ,  G11C16/10 ,  G11C16/16 ,  G11C29/00

CPC classification number: G11C14/0018 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/76 ,  G11C29/785 ,  G11C29/789 ,  G11C29/82 ,  G11C29/84 ,  G11C29/846

Abstract: A non-volatile memory is erasable by page and equipped with a row redundancy mechanism. In the case of the detection of a defective row of the memory plane, the storing of the address of the row in a non-volatile register is carried out and a redundant row having a new address is assigned. In the case of an attempt to write to the defective row, a write to the redundant row is carried out. When writing to the redundant row, the new content of the redundant row is loaded into a volatile memory and, following an operation for writing to any other row of the memory plane, a re-loading of the new content of the redundant row into the volatile memory.

公开(公告)号：US20160336070A1

公开(公告)日：2016-11-17

申请号：US14980853

申请日：2015-12-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/08 ,  G11C16/26 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  G11C16/04 ,  H01L27/115

CPC classification number: G11C16/26 ,  G11C7/18 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/08 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42324

Abstract: Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.

Abstract translation: 包括存储器单元的行和列的非易失性存储器，存储器单元的列包括包括公共选择门的双存储单元对。 根据本公开，每列存储器单元提供两个位线。 相同列的相邻双存储单元不连接到相同的位线，同一列的相邻非双存储单元连接到相同的位线。

公开(公告)号：US09368215B2

公开(公告)日：2016-06-14

申请号：US14810283

申请日：2015-07-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/10 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

Abstract: A method controls a memory that includes twin memory cells formed in a semiconductor substrate. Each memory cell includes a floating-gate transistor including a state control gate, in series with a select transistor that includes a vertical select control gate, common to the twin memory cells, and a source connected to an embedded source line, common to the memory cells. The drains of the floating-gate transistors of the twin memory cells are connected to a same bit line. The method includes controlling a memory cell so as to turn it on to couple the source line to a bit line coupled to the ground, during a step of programming or reading another memory cell.

Abstract translation: 一种方法控制包括形成在半导体衬底中的双存储单元的存储器。 每个存储单元包括一个浮动栅极晶体管，它包括状态控制栅极，与选择晶体管串联，该选择​​晶体管包括双存储单元共用的垂直选择控制栅极和连接到存储器共用的嵌入式源极线路的源极 细胞。 双存储单元的浮栅晶体管的漏极连接到相同的位线。 该方法包括在编程或读取另一个存储器单元的步骤期间控制存储器单元以将其导通以将源极线耦合到耦合到地的位线。

公开(公告)号：US20150348640A1

公开(公告)日：2015-12-03

申请号：US14724229

申请日：2015-05-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/26 ,  H01L21/28 ,  H01L27/115 ,  G11C16/14 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/08 ,  G11C16/14 ,  H01L21/0276 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11524

Abstract: The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.

Abstract translation: 本公开涉及一种半导体衬底上的非易失性存储单元，包括：第一晶体管，包括控制栅极，浮置栅极和漏极区域;第二晶体管，包括控制栅极，浮置栅极和漏极区域， 其中第一和第二晶体管的浮置栅极电耦合，并且第二晶体管包括电耦合到其漏极区域并且通过隧道电介质层与其浮动栅极相对延伸的导电区域。