公开(公告)号：US20050184388A1

公开(公告)日：2005-08-25

申请号：US10782365

申请日：2004-02-19

申请人： Hsin-Ching Shih ,  Kang-Cheng Lin ,  Chao-Cheng Chen ,  Hun-Jan Tao

发明人： Hsin-Ching Shih ,  Kang-Cheng Lin ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L23/48 ,  H01L23/58

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： In accordance with the objective of the invention a new method is provided for the creation of a seal ring having dissimilar elements. The Critical Dimensions of the seal ring are selected with respect to the CD of other device features, such a seal vias, such that the difference in etch sensitivity between the created seal ring and the via holes is removed. All etch of the simultaneously etched features is completed at the same time, avoiding punch through of an underlying layer of etch stop material.

摘要翻译： 根据本发明的目的，提供了一种用于创建具有不同元件的密封环的新方法。 密封环的临界尺寸相对于其它装置特征（例如密封通孔）的CD被选择，使得所产生的密封环和通孔之间的蚀刻敏感性的差异被去除。 同时蚀刻的特征的所有蚀刻同时完成，避免冲蚀下一层蚀刻停止材料。

公开(公告)号：US20050181590A1

公开(公告)日：2005-08-18

申请号：US11101774

申请日：2005-04-08

申请人： Hsien-Kuang Chiu ,  Baw-Ching Perng ,  Hun-Jan Tao

发明人： Hsien-Kuang Chiu ,  Baw-Ching Perng ,  Hun-Jan Tao

IPC分类号： C23F1/00 ,  H01L21/20 ,  H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/78

CPC分类号： H01L21/31144 ,  H01L21/31116

摘要： A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method further includes a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.

摘要翻译： 提供了一种图案化高k介电材料层的方法，其可用于制造半导体器件。 在高k电介质层上进行第一蚀刻。 在第一蚀刻之后，用第一蚀刻蚀刻的高k电介质层的一部分保留。 执行高k电介质层的第二蚀刻以去除高k电介质层的剩余部分。 第二蚀刻不同于第一蚀刻。 优选地，第一蚀刻是干蚀刻工艺，第二蚀刻是湿蚀刻工艺。 该方法还包括在第一次蚀刻之后和第二次蚀刻之前等离子体灰化高k电介质层的剩余部分的工艺。

公开(公告)号：US20050179098A1

公开(公告)日：2005-08-18

申请号：US10780513

申请日：2004-02-17

申请人： Bor-Wen Chan ,  Chih-Hao Wang ,  Lawrance Hsu ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Chih-Hao Wang ,  Lawrance Hsu ,  Hun-Jan Tao

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L29/6659 ,  H01L21/28097 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823857 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/7833

摘要： A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the substrate and the sidewalls of the polysilicon lines. The first isolation layer does not overlie the top surface of the polysilicon lines. The polysilicon lines are partially etched down such that the top surfaces of the polysilicon lines are below the top surface of the first isolation layer. A metal layer is deposited overlying the polysilicon lines. A thermal anneal is used to completely convert the polysilicon lines to metal silicide gates. The unreacted metal layer is removed to complete the device.

摘要翻译： 实现了在制造集成电路器件中形成金属硅化物栅极的新方法。 该方法包括在其间具有介电层的衬底上形成多晶硅线。 第一隔离层形成在衬底和多晶硅线的侧壁上。 第一隔离层不覆盖多晶硅线的顶表面。 多晶硅线被部分地向下蚀刻，使得多晶硅线的顶表面在第一隔离层的顶表面下方。 金属层沉积在多晶硅线上。 使用热退火将多晶硅线完全转换成金属硅化物栅极。 去除未反应的金属层以完成该装置。

公开(公告)号：US20050133830A1

公开(公告)日：2005-06-23

申请号：US10739476

申请日：2003-12-17

申请人： Carlos Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

发明人： Carlos Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/76 ,  H01L31/113

CPC分类号： H01L29/66772 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78621 ,  H01L29/78654

摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.

摘要翻译： 用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。 该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。 根据上述特征，以增强的性能制造场效应晶体管器件。

公开(公告)号：US06864193B2

公开(公告)日：2005-03-08

申请号：US10379769

申请日：2003-03-05

申请人： Chun-Li Chou ,  Hun-Jan Tao ,  Peng-Fu Hsu

发明人： Chun-Li Chou ,  Hun-Jan Tao ,  Peng-Fu Hsu

IPC分类号： C11D7/26 ,  C11D7/50 ,  C11D11/00 ,  H01L21/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/321 ,  H01L21/461

CPC分类号： H01L21/02063 ,  C11D7/261 ,  C11D7/263 ,  C11D7/265 ,  C11D7/267 ,  C11D7/5022 ,  C11D11/0047 ,  Y10S438/905 ,  Y10S438/906

摘要： A composition and method for fabricating a semiconductor wafer containing copper is disclosed, which method includes plasma etching a dielectric layer from the surface of the wafer, plasma ashing a resist from the surface of the wafer, and cleaning the wafer surface by contacting same with a cleaning formulation, which includes the following components and their percentage by weight ranges shown: (a) from about 0.01 to 80% by weight organic solvent, (b) from about 0.01 to 30% by weight copper chelating agent, (c) from about 0.01 to 10% by weight copper inhibitor, and (d) from about 0.01 to 70% by weight water.

摘要翻译： 公开了一种用于制造含有铜的半导体晶片的组合物和方法，该方法包括从晶片的表面等离子体蚀刻介电层，等离子体从晶片的表面灰化抗蚀剂，以及通过使晶片表面与 清洁制剂，其包括以下组分及其重量百分比范围：（a）约0.01至80重量％的有机溶剂，（b）约0.01至30重量％的铜螯合剂，（c）约 0.01〜10重量％的铜抑制剂，（d）约0.01〜70重量％的水。

公开(公告)号：US06828248B1

公开(公告)日：2004-12-07

申请号：US10637350

申请日：2003-08-08

申请人： Hun-Jan Tao ,  Huan-Just Lin

发明人： Hun-Jan Tao ,  Huan-Just Lin

IPC分类号： H01L21302

CPC分类号： H01L21/31116 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76232

摘要： A method of pull back for a shallow trench isolation (STI) structure is provided. The method firstly provides a substrate having a hard mask layer disposed thereupon and a dielectric layer above the hard mask layer. Then a trench is formed within the hard mask layer, the dielectric layer and the substrate. Finally, the hard mask layer and the dielectric layer are pulled back by using a halogen containing etching process.

摘要翻译： 提供了一种用于浅沟槽隔离（STI）结构的拉回方法。 该方法首先提供具有设置在其上的硬掩模层和硬掩模层上方的电介质层的衬底。 然后在硬掩模层，电介质层和衬底内形成沟槽。 最后，通过使用含卤素蚀刻工艺将硬掩模层和电介质层拉回。

公开(公告)号：US06821880B1

公开(公告)日：2004-11-23

申请号：US10725138

申请日：2003-12-01

申请人： Hun-Jan Tao ,  Chao-Cheng Chen

发明人： Hun-Jan Tao ,  Chao-Cheng Chen

IPC分类号： H01L214763

CPC分类号： H01L21/76814 ,  H01L21/67155 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76838

摘要： A process of dual damascene or damascene. The dual damascene process entails providing an etching apparatus, a DCM machine and a wafer, the wafer having a metal line, a stop layer, a dielectric layer, a contact, and a photoresist layer. The dielectric layer and the contact are etched in the etching apparatus to form a trench. The photoresist and the contact are ashed in the DCM machine. Finally the wafer is wet cleaned.

摘要翻译： 一个双镶嵌或镶嵌的过程。 双镶嵌工艺需要提供蚀刻装置，DCM机器和晶片，晶片具有金属线，阻挡层，介电层，接触和光致抗蚀剂层。 在蚀刻装置中蚀刻介电层和接触以形成沟槽。 在DCM机器中将光致抗蚀剂和接触物灰化。 最后将晶片湿式清洗。

公开(公告)号：US06498067B1

公开(公告)日：2002-12-24

申请号：US10139021

申请日：2002-05-02

申请人： Baw-Ching Perng ,  Ming-Huang Tsai ,  Ju-Wang Hsu ,  Hun-Jan Tao

发明人： Baw-Ching Perng ,  Ming-Huang Tsai ,  Ju-Wang Hsu ,  Hun-Jan Tao

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L29/6656

摘要： A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, has been developed. The process features formation of additional insulator spacer shapes on top portions of sides of a gate structure in which an initial insulator spacer had been removed during an over etch cycle used for definition of the initial insulator spacer. The re-establishment of insulator spacer shapes provides a composite insulator spacer offering reduced risk of gate to substrate leakage or shorts, that can occur during a subsequent salicide procedure from the presence of metal silicide stringers or ribbons formed on, and residing on the composite insulator spacer.

摘要翻译： 已经开发了在MOSFET栅极结构的侧面上形成复合绝缘体间隔物的工艺。 该工艺特征是在栅极结构的侧面的顶部部分上形成额外的绝缘体间隔物形状，其中在用于限定初始绝缘体间隔物的过蚀刻循环期间已经去除了初始绝缘体间隔物。 重新建立绝缘体间隔物形状提供了一种复合绝缘体间隔物，其降低了栅极与衬底泄漏或短路的风险，这可能在随后的自对准硅化物过程中发生，从存在金属硅化物桁条或形成在复合绝缘体上的带状物 间隔

公开(公告)号：US06472335B1

公开(公告)日：2002-10-29

申请号：US09175019

申请日：1998-10-19

申请人： Chia-Shiung Tsai ,  Yao-Yi Cheng ,  Hun-Jan Tao

发明人： Chia-Shiung Tsai ,  Yao-Yi Cheng ,  Hun-Jan Tao

IPC分类号： H01L2131

CPC分类号： H01L21/0214 ,  H01L21/02118 ,  H01L21/022 ,  H01L21/02343 ,  H01L21/31111 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/3124 ,  H01L21/3144 ,  H01L21/31629 ,  H01L21/3185 ,  H01L21/76801 ,  Y10S438/906 ,  Y10S438/958 ,  Y10S438/964

摘要： The present invention provides a method improving the adhesion between inter metal dielectric (IMD) layers by performing a HF dip etch to treat the surface of an oxide, silicon nitride or Silicon oxynitride insulating layer before an overlying low-K layer is formed. The present invention provides a method of fabricating a low-K IMD layer 20 over an oxide, Silicon oxynitride (SiON), or nitride IMD layer 14 with improved adhesion. First, a 1st inter metal dielectric (IMD) layer 14 is formed over a substrate. Next, the invention's novel HF dip etch is performed on the 1st IMD layer 14 to form a treated surface 16. Next, a 2nd BMD layer composed of a low-K material is formed over the rough surface 16 of the 1st IMD layer 14. The treated surface 16 improves the adhesion between a 1st IMD layer oxide (oxide, SiN or SiON) and a low k layer. Subsequent photoresist strip steps do not cause the 1st IMI layer 14 and the 2nd IMD layer 20 (low-K dielectric) to peel.

摘要翻译： 本发明提供一种通过在形成上覆低K层之前进行HF浸渍蚀刻来处理氧化物，氮化硅或氮氧化硅绝缘层的表面来改善金属间电介质（IMD）层之间的粘合力的方法。 本发明提供了一种在氧化物，氮氧化硅（SiON）或氮化物IMD层14上制备低K IMD层20的方法，其具有改善的粘合性。 首先，在衬底上形成第一金属间介电层（IMD）层14。 接下来，在第一IMD层14上进行本发明的新型HF浸渍蚀刻以形成处理表面16.接下来，在第一IMD层14的粗糙表面16上形成由低K材料构成的第二BMD层。 经处理的表面16改善了第一IMD层氧化物（氧化物，SiN或SiON）和低k层之间的粘合性。 随后的光刻胶条步骤不会导致第一IMI层14和第二IMD层20（低K电介质）剥离。

公开(公告)号：US06410424B1

公开(公告)日：2002-06-25

申请号：US09837599

申请日：2001-04-19

申请人： Ming-Huan Tsai ,  Chung-Long Chang ,  Chii-Ming Wu ,  Hun-Jan Tao

发明人： Ming-Huan Tsai ,  Chung-Long Chang ,  Chii-Ming Wu ,  Hun-Jan Tao

IPC分类号： H01L214763

CPC分类号： H01L21/76804 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76829 ,  H01L21/76831 ,  Y10S438/975

摘要： A new processing sequence is provided for the creation of openings in layers of dielectric. Over a semiconductor surface are successively deposited an etch stop layer, a layer of dielectric and a hard mask layer. An opening is etched in the hard mask layer, the main opening is etched through the layer of dielectric and the etch stop layer. The surface is wet cleaned, after which a thin layer of silicon oxide is CVD deposited over the inside surfaces of the created opening. This thin layer of CVD oxide is subjected to argon sputter, providing of the critical dimensions of the upper region of the opening. Then the process continues with the deposition of the barrier metal, the filling of the opening with a conducting material to create the metal plug and the polishing of the surface of the deposited conducting material.

摘要翻译： 提供了一种新的处理顺序，用于在电介质层中产生开口。 在半导体表面上依次沉积蚀刻停止层，电介质层和硬掩模层。 在硬掩模层中蚀刻开口，通过电介质层和蚀刻停止层蚀刻主开口。 表面被湿清洗，之后在所产生的开口的内表面上CVD沉积薄层的氧化硅。 对CVD氧化物薄层进行氩溅射，提供开口上部区域的临界尺寸。 然后，该过程继续阻挡金属的沉积，用导电材料填充开口以产生金属塞和抛光沉积的导电材料的表面。