公开(公告)号：US12167606B2

公开(公告)日：2024-12-10

申请号：US17459107

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chi On Chui

IPC: H10B51/20 ,  H01L29/786 ,  H10B51/10 ,  H10B53/20

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line, an oxide semiconductor (OS) layer contacting a source line and a bit line, and a conductive feature interposed between the memory film and the OS layer. The memory film is disposed between the OS layer and the word line. A dielectric material covers sidewalls of the source line, the memory film, and the OS layer.

公开(公告)号：US12159922B2

公开(公告)日：2024-12-03

申请号：US18301704

申请日：2023-04-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78

Abstract: A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a sidewall of the dummy gate. The dummy gate is replaced with a gate structure. A top portion of the first spacer is removed. After the top portion of the first spacer is removed, a second spacer is over the first spacer. The second spacer has a stepped bottom surface with an upper step in contact with a top surface of the first spacer and a lower step lower than the top surface of the first spacer. A contact plug is formed contacting the gate structure and the second spacer.

公开(公告)号：US20240387534A1

公开(公告)日：2024-11-21

申请号：US18787838

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Li-Zhen Yu ,  Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/027 ,  H01L21/306 ,  H01L21/308

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

公开(公告)号：US12148505B2

公开(公告)日：2024-11-19

申请号：US18362685

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: G11C8/14 ,  H01L21/822 ,  H10B51/20 ,  H10B99/00

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

公开(公告)号：US12119390B2

公开(公告)日：2024-10-15

申请号：US17858968

申请日：2022-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Clement Hsingjen Wann ,  Kuo-Feng Yu ,  Ming-Hsi Yeh ,  Shahaji B. More ,  Yu-Ming Lin

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/51

CPC classification number: H01L29/6656 ,  H01L21/28194 ,  H01L21/823462 ,  H01L21/823468 ,  H01L29/518

Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.

公开(公告)号：US20240334708A1

公开(公告)日：2024-10-03

申请号：US18742325

申请日：2024-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-I Wu ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H10B51/30 ,  H01L21/02 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20

CPC classification number: H10B51/30 ,  H01L21/02565 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78391 ,  H10B51/20

Abstract: A memory device includes: a first layer stack and a second layer stack formed successively over a substrate, where each of the first and the second layer stacks includes a first metal layer, a second metal layer, and a first dielectric material between the first and the second metal layers; a second dielectric material between the first and the second layer stacks; a gate electrode extending through the first and the second layer stacks, and through the second dielectric material; a ferroelectric material extending along and contacting a sidewall of the gate electrode; and a channel material, where a first portion and a second portion of the channel material extend along and contact a first sidewall of the first layer stack and a second sidewall of the second layer stack, respectively, where the first portion and the second portion of the channel material are separated from each other.

公开(公告)号：US12087860B2

公开(公告)日：2024-09-10

申请号：US17412032

申请日：2021-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/02 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02532 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method includes providing a semiconductor structure having metal gate structures (MGs), gate spacers disposed on sidewalls of the MGs, and source/drain (S/D) features disposed adjacent to the gate spacers; forming a first dielectric layer over the MGs and forming S/D contacts (MDs) over the S/D features; forming a second dielectric layer over the first dielectric layer, where portions of the second dielectric layer contact the MDs and the second dielectric layer is different from the first dielectric layer in composition; removing the portions of the second dielectric layer that contact the MDs; forming a conductive layer over the MDs and over the first dielectric layer; and removing portions of the conductive layer to form conductive features over the MDs.

公开(公告)号：US20240276726A1

公开(公告)日：2024-08-15

申请号：US18632806

申请日：2024-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Feng-Cheng Yang ,  Sheng-Chen Wang ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H10B43/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A memory array device includes a stack of transistors over a semiconductor substrate, a first transistor of the stack being disposed over a second transistor of the stack. The first transistor includes a first memory film along a first word line and a first channel region along a source line and a bit line, the first memory film being disposed between the first channel region and the first word line. The second transistor includes a second memory film along a second word line and a second channel region along the source line and the bit line, the second memory film being disposed between the second channel region and the second word line. The memory array device includes a first via electrically connected to the first word line and a second via electrically connected to the second word line, the second staircase via and the first staircase via having different widths.

公开(公告)号：US20240274160A1

公开(公告)日：2024-08-15

申请号：US18644516

申请日：2024-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chenchen Jacob Wang ,  Yi-Ching Liu ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Yih Wang

IPC: G11C5/06 ,  H01L29/24 ,  H01L29/78 ,  H01L29/786 ,  H10B41/27 ,  H10B51/00 ,  H10B51/10 ,  H10B51/20

CPC classification number: G11C5/063 ,  H01L29/24 ,  H01L29/78391 ,  H01L29/7869 ,  H10B41/27 ,  H10B51/00 ,  H10B51/10 ,  H10B51/20

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material contacting a first word line; an oxide semiconductor (OS) layer contacting a source line and a bit line, the FE material being disposed between the OS layer and the first word line; a dielectric material contacting the FE material, the FE material being between the dielectric material and the first word line; an inter-metal dielectric (IMD) over the first word line; a first contact extending through the IMD to the first word line, the first contact being electrically coupled to the first word line; a second contact extending through the dielectric material and the FE material; and a first conductive line electrically coupling the first contact to the second contact.

公开(公告)号：US12057398B2

公开(公告)日：2024-08-06

申请号：US17871272

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Sheng-Tsung Wang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L23/53295 ,  H01L21/7682 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/785

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.