公开(公告)号：US20190128958A1

公开(公告)日：2019-05-02

申请号：US16232373

申请日：2018-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Chao-Hsiang Yang

IPC: G01R31/28 ,  H01L21/66 ,  G01R1/04 ,  G01R31/26 ,  H01L23/00

CPC classification number: G01R31/2896 ,  G01R1/0416 ,  G01R31/2601 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02377 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/0614 ,  H01L2224/0616 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16238 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.

公开(公告)号：US10153205B2

公开(公告)日：2018-12-11

申请号：US14990976

申请日：2016-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shang-Yun Hou ,  Wen-Chih Chiou ,  Jui-Pin Hung ,  Der-Chyang Yeh ,  Chiung-Han Yeh

IPC: H01L21/78 ,  H01L49/02 ,  H01L27/12 ,  H01L27/32 ,  H01L23/00 ,  H01L23/522 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/525

Abstract: A package includes a chip that has a metal-insulator-metal (MIM) capacitor formed in a first polymer layer and a metallic pillar formed on the MIM capacitor. A molding compound surrounds the chip, a second polymer layer is formed on the chip and the molding compound, a third polymer layer is formed on the second polymer layer, an interconnect structure is formed between the second polymer layer and the third polymer layer and electrically coupled to the metallic pillar and the MIM capacitor, and a bump is formed over and electrically coupled to the interconnect structure.

公开(公告)号：US09818720B2

公开(公告)日：2017-11-14

申请号：US14981458

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hsin Wei ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Wei-Ming Chen

IPC: H01L23/34 ,  H01L23/52 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H05K3/36 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H05K3/363

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a first chip structure and a second chip structure. Heights of the first chip structure and the second chip structure are different. The chip package also includes a package layer covering sidewalls of the first chip structure and sidewalls of the second chip structure. Top surfaces of the first chip structure and the second chip structure are not covered by the package layer.

公开(公告)号：US12243824B2

公开(公告)日：2025-03-04

申请号：US18525958

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu

IPC: H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.

公开(公告)号：US20240385395A1

公开(公告)日：2024-11-21

申请号：US18467020

申请日：2023-09-14

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Ming-Fa Chen ,  Shang-Yun Hou

IPC: G02B6/42

Abstract: In an embodiment, a method includes: forming an optical package, forming the optical package comprising: forming optical devices over a substrate; forming a first interconnect structure over the optical devices; and attaching a first semiconductor device to the optical devices; attaching a second semiconductor device to an interposer substrate; attaching the optical package to the interposer substrate; and attaching an optical port adjacent to the optical package, the optical port comprising: an optical fiber; and an optical redirection structure configured to redirect an optical signal between a first pathway and a second pathway, the first pathway being parallel with a major surface of the interposer substrate, the second pathway being non-parallel with the major surface of the interposer substrate.

公开(公告)号：US20240310733A1

公开(公告)日：2024-09-19

申请号：US18334650

申请日：2023-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Chien-Hsun Lee ,  Tsung-Ding Wang ,  Hao-Cheng Hou

IPC: G03F7/20 ,  H01L21/48 ,  H01L23/538

CPC classification number: G03F7/2022 ,  H01L21/4857 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/0655

Abstract: A method includes forming a photoresist on a base structure, and performing a first light-exposure process on the photoresist using a first lithography mask. In the first light-exposure process, an inner portion of the photoresist is blocked from being exposed, and a peripheral portion of the photoresist is exposed. The peripheral portion encircles the inner portion. A second light-exposure process is performed on the photoresist using a second lithography mask. In the second light-exposure process, the inner portion of the photoresist is exposed, and the peripheral portion of the photoresist is blocked from being exposed. The photoresist is then developed.

公开(公告)号：US12087733B2

公开(公告)日：2024-09-10

申请号：US17383911

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Yu Huang ,  Li-Chung Kuo ,  Sung-Hui Huang ,  Shang-Yun Hou

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0655 ,  H01L23/3185 ,  H01L23/49833 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/92 ,  H01L25/50 ,  H01L25/18 ,  H01L2224/32057 ,  H01L2224/33051 ,  H01L2224/33152 ,  H01L2224/3316 ,  H01L2224/73204 ,  H01L2224/9211 ,  H01L2224/92125

Abstract: A method includes bonding a first package component over a second package component, dispensing a first underfill between the first package component and the second package component, and bonding a third package component over the second package component. A second underfill is between the third package component and the second package component. The first underfill and the second underfill are different types of underfills.

公开(公告)号：US11996371B2

公开(公告)日：2024-05-28

申请号：US17339745

申请日：2021-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Weiming Chris Chen ,  Kuo-Chiang Ting ,  Hsien-Pin Hu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L21/56 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/6835 ,  H01L2224/16227 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.

公开(公告)号：US11852868B2

公开(公告)日：2023-12-26

申请号：US17873779

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: G02B6/122 ,  G02B6/12

CPC classification number: G02B6/1225 ,  G02B6/12019 ,  G02B2006/1213

Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.

公开(公告)号：US20230378132A1

公开(公告)日：2023-11-23

申请号：US18150525

申请日：2023-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Wei Shen ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Sen-Bor Jan ,  Szu-Po Huang ,  Kuan-Yu Huang

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/0655 ,  H01L21/565 ,  H01L21/563 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/05 ,  H01L21/76895 ,  H01L23/49827 ,  H01L2224/05569 ,  H01L2224/16146 ,  H01L2924/3511 ,  H01L24/16

Abstract: A semiconductor device includes: a substrate; a plurality of dies attached to a first side of the substrate; a molding material on the first side of the substrate around the plurality of dies; a first redistribution structure on a second side of the substrate opposing the first side, where the first redistribution structure includes dielectric layers and conductive features in the dielectric layers, where the conductive features include conductive lines, vias, and dummy metal patterns isolated from the conductive lines and the vias; and conductive connectors attached to a first surface of the first redistribution structure facing away from the substrate.