中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

146 records (took 0.023 seconds)

    SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
    81.
    发明申请
    SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 审中-公开
    半导体结构及其制造方法

    公开(公告)号：US20150014808A1

    公开(公告)日：2015-01-15

    申请号：US13939204

    申请日：2013-07-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Hung Tsai ,  Rai-Min Huang ,  I-Ming Tseng ,  Yu-Ting Lin ,  Chien-Ting Lin

    IPC: H01L21/762 ,  H01L21/311 ,  H01L29/06

    CPC classification number: H01L21/76224 ,  H01L21/02236 ,  H01L21/3065 ,  H01L21/3086 ,  H01L29/66818 ,  H01L29/7853

    Abstract: A fabrication method for a semiconductor structure at least includes the following steps. First, a pattern mask with a predetermined layout pattern is formed on a substrate. The layout pattern is then transferred to the underneath substrate so as to form at least a fin-shaped structure in the substrate. Subsequently, a shallow trench isolation structure is formed around the fin-shaped structure. Afterwards, a steam oxidation process is carried out to oxidize the fin-shaped structure protruding from the shallow trench isolation and to form an oxide layer on its surface. Finally, the oxide layer is removed completely.

    Abstract translation: 半导体结构的制造方法至少包括以下步骤。 首先，在基板上形成具有预定布局图案的图案掩模。 然后将布局图案转移到基底下方，以在基底中形成至少一个鳍状结构。 随后，在鳍状结构周围形成浅沟槽隔离结构。 之后，进行蒸汽氧化处理，使从浅沟槽隔离突出的鳍状结构氧化，并在其表面形成氧化物层。 最后，氧化层被完全去除。

    SEMICONDUCTOR PROCESS
    82.
    发明申请
    SEMICONDUCTOR PROCESS 有权
    半导体工艺

    公开(公告)号：US20140363935A1

    公开(公告)日：2014-12-11

    申请号：US13912218

    申请日：2013-06-07

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ssu-I Fu ,  Cheng-Guo Chen ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Chien-Ting Lin

    IPC: H01L29/66

    CPC classification number: H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848

    Abstract: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and a gate structure partially overlapping the fin-shaped structure is formed. Subsequently, a dielectric layer is blanketly formed on the substrate, and a part of the dielectric layer is removed to form a first spacer on the fin-shaped structure and a second spacer besides the fin-shaped structure. Furthermore, the second spacer and a part of the fin-shaped structure are removed to form at least a recess at a side of the gate structure, and an epitaxial layer is formed in the recess.

    Abstract translation: 半导体工艺包括以下步骤。 提供基板。 至少在基板上形成翅片状结构，形成与翅片状结构部分重叠的栅极结构。 随后，在衬底上覆盖地形成电介质层，除去电介质层的一部分，以在鳍状结构上形成第一间隔物，除了鳍状结构之外还形成第二间隔物。 此外，去除第二间隔件和鳍状结构的一部分以在栅极结构的一侧形成至少一个凹部，并且在凹部中形成外延层。

    METHOD OF FORMING SEMICONDUCTOR DEVICE
    83.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICE 有权
    形成半导体器件的方法

    公开(公告)号：US20140295660A1

    公开(公告)日：2014-10-02

    申请号：US14302047

    申请日：2014-06-11

    Applicant: United Microelectronics Corp.

    Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Chien-Ting Lin ,  Wen-Tai Chiang

    IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/28

    CPC classification number: H01L29/6681 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/283 ,  H01L21/76224 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

    Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally foamed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.

    Abstract translation: 提供一种形成半导体器件的方法。 通过在衬底上的沉积工艺形成第一界面材料层。 在第一界面材料层上形成虚拟栅极材料层。 将虚拟栅材料层和第一界面材料层图案化以形成堆叠结构。 形成层间电介质（ILD）层以覆盖层叠结构。 去除ILD层的一部分以露出堆叠结构的顶部。 去除层叠结构以在ILD层中形成沟槽。 第二界面层和第一高k层至少在沟槽的表面上保形发泡。 复合金属层形成为至少填充沟槽。

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    84.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
    半导体器件及其形成方法

    公开(公告)号：US20140264480A1

    公开(公告)日：2014-09-18

    申请号：US13802878

    申请日：2013-03-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Chao Tsao ,  Chien-Ting Lin

    IPC: H01L23/538 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L23/5384 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a semiconductor device includes the following steps. At first, a semiconductor substrate is provided, and a metal gate structure and a first dielectric layer are disposed on the semiconductor substrate, wherein a top surface of the metal gate structure is aligned with a top surface of the first dielectric layer. Then, a patterned mask is formed on the metal gate structure, and the patterned mask does not overlap the first dielectric layer. Subsequently, a second dielectric layer covering the patterned mask is conformally formed on the semiconductor substrate. Furthermore, a part of the first dielectric layer and a part of the second dielectric layer are removed for forming at least a contact hole.

    Abstract translation: 形成半导体器件的方法包括以下步骤。 首先，提供半导体衬底，并且在半导体衬底上设置金属栅极结构和第一电介质层，其中金属栅极结构的顶表面与第一电介质层的顶表面对齐。 然后，在金属栅极结构上形成图案化掩模，并且图案化掩模不与第一介电层重叠。 随后，覆盖图案化掩模的第二电介质层共形地形成在半导体衬底上。 此外，除去第一电介质层的一部分和第二电介质层的一部分以至少形成接触孔。

    METHOD FOR FORMING FIN-SHAPED STRUCTURE
    85.
    发明申请
    METHOD FOR FORMING FIN-SHAPED STRUCTURE 有权
    形成精细结构的方法

    公开(公告)号：US20140235043A1

    公开(公告)日：2014-08-21

    申请号：US13772343

    申请日：2013-02-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chien-Ting Lin ,  Shih-Hung Tsai

    IPC: H01L21/28

    CPC classification number: H01L29/7853 ,  H01L29/66795

    Abstract: A method for forming a fin-shaped structure includes the following steps. A pad layer is formed on a substrate. A sacrificial pattern is formed on the pad layer. A spacer is formed on the pad layer beside the sacrificial pattern, wherein the ratio of the height of the spacer to the pad layer is larger than 5. The sacrificial pattern is removed. The layout of the spacer is transferred to the substrate to form at least a fin-shaped structure having a taper profile in the substrate.

    Abstract translation: 形成翅片状结构的方法包括以下步骤。 衬底层形成在衬底上。 牺牲图案形成在衬垫层上。 在牺牲图案旁边的垫层上形成间隔物，其中间隔物与垫层的高度比大于5.牺牲图案被去除。 间隔物的布局被转移到基底以至少形成在基底中具有锥形轮廓的鳍状结构。

    Non-planar semiconductor structure
    86.
    发明授权
    Non-planar semiconductor structure 有权
    非平面半导体结构

    公开(公告)号：US08779513B2

    公开(公告)日：2014-07-15

    申请号：US13869037

    申请日：2013-04-24

    Applicant: United Microelectronics Corp.

    Inventor： Shih-Hung Tsai ,  Chien-Ting Lin ,  Chin-Cheng Chien ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chun-Yuan Wu

    IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L29/66795

    Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.

    Abstract translation: 非平面半导体结构包括衬底，至少两个鳍状结构，至少一个隔离结构和多个外延层。 鳍状结构位于基底上。 隔离结构位于鳍状结构之间，隔离结构具有含氮层。 外延层分别覆盖了鳍状结构的一部分并且位于含氮层上。 还提供了用于形成半导体结构的非平面半导体工艺。

    Method for fabricating semiconductor device
    87.
    发明授权
    Method for fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08748278B2

    公开(公告)日：2014-06-10

    申请号：US14069179

    申请日：2013-10-31

    Applicant: United Microelectronics Corp.

    Inventor： Chang-Tzu Wang ,  Mei-Ling Chao ,  Chien-Ting Lin

    IPC: H01L21/336

    CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/823821 ,  H01L27/0924

    Abstract: A method for fabricating a semiconductor device is provided. A fin of a first conductivity type is formed on a substrate of the first conductivity type. A gate is formed on the substrate, wherein the gate covers a portion of the fin. Source and drain regions of a second conductivity type are formed in the fin at respective sides of the gate. A punch-through stopper (PTS) of the first conductivity type is formed in the fin underlying the gate and between the source and drain regions, wherein the PTS has an impurity concentration higher than that of the substrate. A first impurity of the second conductivity type is implanted into the PTS, so as to compensate the impurity concentration of the PTS.

    Abstract translation: 提供一种制造半导体器件的方法。 在第一导电类型的衬底上形成第一导电类型的鳍。 栅极形成在衬底上，其中栅极覆盖鳍片的一部分。 第二导电类型的源极和漏极区域形成在栅极的相应侧的翅片中。 第一导电类型的穿通止动件（PTS）形成在栅极下方的栅极和源极和漏极区域之间，其中PTS的杂质浓度高于衬底的杂质浓度。 将第二导电类型的第一杂质注入到PTS中，以补偿PTS的杂质浓度。

Patent Agency Ranking