公开(公告)号：US08877555B2

公开(公告)日：2014-11-04

申请号：US13678847

申请日：2012-11-16

Applicant: Lei Shi ,  Yan Xun Xue ,  Yuping Gong

Inventor： Lei Shi ,  Yan Xun Xue ,  Yuping Gong

IPC: H01L21/56 ,  H01L23/00

CPC classification number: H01L21/561 ,  H01L21/4832 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92247 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected.

Abstract translation: 公开了专门用于倒装芯片垂直功率器件的封装半导体器件的制备方法。 在这些方法中，将垂直半导体芯片倒装芯片连接到引线框架，然后用塑料包装材料封装。 然后将封装的芯片变薄到预定厚度。 通过蚀刻至少连接的引线框架的底部部分，形成连接芯片与外部电路的接触端子。

公开(公告)号：US20140319601A1

公开(公告)日：2014-10-30

申请号：US13871144

申请日：2013-04-26

Applicant: Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

Inventor： Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L29/42372 ,  H01L29/781 ,  H01L2224/04105 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/051 ,  H01L2224/05562 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface.

Abstract translation: 底部源极功率金属氧化物半导体场效应晶体管（MOSFET）器件包括形成在半导体芯片的第一表面上的初始绝缘层上的栅电极和源电极，以及形成在半导体芯片的第二表面上的漏电极 半导体芯片 源电极包括源极金属，形成在源极金属上的源极电极凸点和源极电极凸起顶部上的源电极金属层。 第一绝缘层覆盖栅电极。 从芯片的第二表面形成与栅电极对准的贯通孔，以将栅电极的一部分从第二表面露出。

公开(公告)号：US08785296B2

公开(公告)日：2014-07-22

申请号：US13396531

申请日：2012-02-14

Applicant: Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho

Inventor： Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho

IPC: H01L21/46 ,  H01L21/00

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/94 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00015

Abstract: A packaging method with backside wafer dicing includes the steps of forming a support structure at the front surface of the wafer then depositing a metal layer on a center area of the backside of the wafer after grinding the wafer backside to reduce the wafer thickness; detecting from the backside of the wafer sections of scribe lines formed in the front surface in the region between the edge of the metal layer and the edge of the wafer and cutting the wafer and the metal layer from the wafer backside along a straight line formed by extending a scribe line section detected from the wafer backside.

Abstract translation: 具有背面晶片切割的封装方法包括以下步骤：在晶片的前表面形成支撑结构，然后在晶片背面研磨之后在晶片背面的中心区域沉积金属层以减小晶片厚度; 从形成在金属层的边缘与晶片边缘之间的区域中的前表面的划线的背面检测，并从晶片背面沿着直线形成的直线切割晶片和金属层， 延伸从晶片背面检测的划线部分。

公开(公告)号：US08722467B2

公开(公告)日：2014-05-13

申请号：US13539304

申请日：2012-06-30

Applicant: Lei Shi ,  Aihua Lu ,  Yan Xun Xue

Inventor： Lei Shi ,  Aihua Lu ,  Yan Xun Xue

IPC: H01L21/50 ,  H01L21/60 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L21/50 ,  H01L23/495 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/14 ,  H01L24/17 ,  H01L24/32 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A die attach method for a semiconductor chip with a back metal layer located at the back surface of the semiconductor chip comprises the steps of forming a bonding ball array including a plurality of bonding balls with a same height on a die attach area at a top surface of a die paddle; depositing a die attach material in the bonding ball array area with a thickness of the die attach material equal or slightly larger than the height of the bonding ball; attaching the semiconductor chip to the die attach area at the top surface of the die paddle by the die attach material, wherein the bonding ball array controls the bond line thickness of the die attach material between the back metal layer and the top surface of the die paddle and prevents the semiconductor chip from rotating on the die attach material when it is melted.

Abstract translation: 具有位于半导体芯片的背面的背面金属层的半导体芯片的芯片贴附方法包括以下步骤：在上表面的芯片附着区域上形成包括具有相同高度的多个接合球的接合球阵列 的模具 在焊接球阵列区域中沉积管芯附着材料，其中管芯附着材料的厚度等于或略大于焊接球的高度; 将所述半导体芯片通过所述芯片附着材料附接到所述芯片的顶表面处的所述芯片附着区域，其中，所述接合球阵列控制所述芯片附着材料在所述背面金属层与所述模具的顶表面之间的结合线厚度 并且防止半导体芯片在熔融时在芯片附着材料上旋转。

公开(公告)号：US20140001617A1

公开(公告)日：2014-01-02

申请号：US13539304

申请日：2012-06-30

Applicant: Lei Shi ,  Aihua Lu ,  Yan Xun Xue

Inventor： Lei Shi ,  Aihua Lu ,  Yan Xun Xue

IPC: H01L21/50 ,  H01L23/495

CPC classification number: H01L24/11 ,  H01L21/50 ,  H01L23/495 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/14 ,  H01L24/17 ,  H01L24/32 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A die attach method for a semiconductor chip with a back metal layer located at the back surface of the semiconductor chip comprises the steps of forming a bonding ball array including a plurality of bonding balls with a same height on a die attach area at a top surface of a die paddle; depositing a die attach material in the bonding ball array area with a thickness of the die attach material equal or slightly larger than the height of the bonding ball; attaching the semiconductor chip to the die attach area at the top surface of the die paddle by the die attach material, wherein the bonding ball array controls the bond line thickness of the die attach material between the back metal layer and the top surface of the die paddle and prevents the semiconductor chip from rotating on the die attach material when it is melted.

Abstract translation: 具有位于半导体芯片的背面的背面金属层的半导体芯片的芯片贴附方法包括以下步骤：在上表面的芯片附着区域上形成包括具有相同高度的多个接合球的接合球阵列 的模具 在焊接球阵列区域中沉积管芯附着材料，其中管芯附着材料的厚度等于或略大于焊接球的高度; 将所述半导体芯片通过所述芯片附着材料附接到所述芯片的顶表面处的所述芯片附着区域，其中，所述接合球阵列控制所述芯片附着材料在所述背面金属层与所述模具的顶表面之间的结合线厚度 并且防止半导体芯片在熔融时在芯片附着材料上旋转。

公开(公告)号：US08569169B2

公开(公告)日：2013-10-29

申请号：US13273219

申请日：2011-10-13

Applicant: Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

Inventor： Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

IPC: H01L21/44

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L29/781 ,  H01L2224/04105 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/051 ,  H01L2224/05562 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface.

Abstract translation: 底部源极功率金属氧化物半导体场效应晶体管（MOSFET）器件包括形成在半导体芯片的第一表面上的初始绝缘层上的栅电极和源电极，以及形成在半导体芯片的第二表面上的漏电极 半导体芯片 源电极包括源极金属，形成在源极金属上的源极电极凸点和源极电极凸起顶部上的源电极金属层。 第一绝缘层覆盖栅电极。 从芯片的第二表面形成与栅电极对准的贯通孔，以将栅电极的一部分从第二表面露出。

公开(公告)号：US20130037962A1

公开(公告)日：2013-02-14

申请号：US13429263

申请日：2012-03-23

Applicant: Yan Xun Xue

Inventor： Yan Xun Xue

IPC: H01L23/48 ,  H01L21/78

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/03

Abstract: A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.

Abstract translation: 一种用于提供具有增加的接触焊盘区域的晶片级封装的方法，包括以下步骤：在晶片顶表面上形成第一封装层，研磨晶片背面并蚀刻通孔，沉积金属以填充通孔并覆盖晶片背面， 从晶片背面切割晶片，形成分开每个芯片的多个沟槽，然后沉积填充沟槽并覆盖晶片背面金属的第二封装层，减小第一封装层厚度以露出填充凹槽的第二封装层并形成多个 接触垫重叠在第一包装层上，然后切割槽中的第二包装层以形成单个包装。

公开(公告)号：US08163601B2

公开(公告)日：2012-04-24

申请号：US12894105

申请日：2010-09-29

Applicant: Yuping Gong ,  Yan Xun Xue

Inventor： Yuping Gong ,  Yan Xun Xue

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L23/49562 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0346 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/3701 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/83191 ,  H01L2224/8485 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1816 ,  H01L2924/01028 ,  H01L2224/03 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chip on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices.

Abstract translation: 一种制造芯片暴露半导体封装的方法，包括以下步骤：在晶片上的每个芯片的正面上电镀多个电极; 研磨晶片的背面并沉积后金属，然后分离每个芯片; 安装具有粘附在引线框架的多个桨叶的前面上的电镀电极的芯片; 将胶带粘附在背面金属上并用模塑料包封; 移除带子并穿过引线框架和模塑料形成多个封装的半导体器件。

公开(公告)号：US08853003B2

公开(公告)日：2014-10-07

申请号：US13602144

申请日：2012-09-01

Applicant: Yan Xun Xue

Inventor： Yan Xun Xue

IPC: H01L23/495 ,  H01L21/60 ,  H01L21/56 ,  H01L23/492 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49827 ,  H01L21/561 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05025 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/32245 ,  H01L2224/73104 ,  H01L2224/73153 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices.

Abstract translation: 一种形成具有厚底金属的晶片级芯片级（WLCS）封装器件的方法，包括将包括多个厚底金属的引线框架附接到半导体晶片的背金属层上的步骤，该半导体晶片包括多个半导体芯片， 形成在每个芯片的前表面上的多个接合焊盘，每个厚的底部金属与每个芯片的中心部分对准; 沿着划线形成多个后侧切割槽并填充有封装材料，从而切割包装材料从而形成多个单个WLCS封装装置。

公开(公告)号：US20140242756A1

公开(公告)日：2014-08-28

申请号：US13775212

申请日：2013-02-24

Applicant: Yan Xun Xue ,  Ping Huang ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Lei Shi ,  Liang Zhao ,  Ping Li Wu ,  Lei Duan ,  Yuping Gong

Inventor： Yan Xun Xue ,  Ping Huang ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Lei Shi ,  Liang Zhao ,  Ping Li Wu ,  Lei Duan ,  Yuping Gong

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/73 ,  H01L2224/1184 ,  H01L2224/13101 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/29 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/83191 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/13091 ,  H01L2924/18301 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method for preparing semiconductor devices in a flip chip process comprises forming deep grooves surrounding each of the semiconductor chips; depositing a first plastic package material to form a first plastic package layer covering front surface of the semiconductor wafer and filling the deep grooves; depositing a metal layer at back surface of the semiconductor wafer after grinding; grinding an outermost portion of the metal layer thus forming a ring area located at back surface around edge of the semiconductor wafer not covered by the metal layer; cutting the first plastic package layer, the semiconductor wafer, the metal layer and the first plastic package material filled in the deep grooves along a straight line formed by two ends of each of the deep grooves filled with the first plastic package material; and picking up the semiconductor devices and mounting on a substrate without flipping the semiconductor devices.

Abstract translation: 一种用于在倒装芯片工艺中制备半导体器件的方法包括形成围绕每个半导体芯片的深槽; 沉积第一塑料封装材料以形成覆盖半导体晶片的前表面并填充深槽的第一塑料封装层; 在研磨后在半导体晶片的背面沉积金属层; 研磨金属层的最外部分，从而形成位于未被金属层覆盖的半导体晶片的边缘周围的背面的环形区域; 沿着由填充有第一塑料包装材料的每个深槽的两端形成的直线切割填充在深槽中的第一塑料封装层，半导体晶片，金属层和第一塑料封装材料; 并且拾取半导体器件并安装在衬底上，而不会翻转半导体器件。