公开(公告)号：US08911636B2

公开(公告)日：2014-12-16

申请号：US14040698

申请日：2013-09-29

Applicant: Viswanadam Gautham

Inventor： Viswanadam Gautham

IPC: C23F1/00 ,  B44C1/22 ,  B81C1/00 ,  H01L21/00

CPC classification number: B81C1/00341 ,  B81B2201/051 ,  B81B2203/0315 ,  B81B2203/0338 ,  B81C1/00476 ,  B81C2201/0107 ,  B81C2203/036 ,  H01L21/00

Abstract: A method of fabricating a micro-device having micro-features on glass is presented. The method includes the steps of preparing a first glass substrate, fabricating a metallic pattern on the first glass substrate, preparing a second glass substrate and providing one or more apertures on the second glass substrate, heating the first glass substrate and the second glass substrate with a controlled temperature raise, bonding the first glass substrate and the second glass substrate by applying pressure to form a bonded substrate, wherein the metallic pattern is embedded within the bonded substrate, cooling the bonded substrate with a controlled temperature drop and thereafter maintaining the bonded substrate at a temperature suitable for etching, etching the metallic pattern within the bonded substrate, wherein an etchant has access to the metallic pattern via the apertures, forming a void within the bonded substrate, wherein the void comprises micro-features.

Abstract translation: 提出了一种在玻璃上制造具有微特征的微器件的方法。 该方法包括以下步骤：制备第一玻璃基板，在第一玻璃基板上制造金属图案，制备第二玻璃基板并在第二玻璃基板上提供一个或多个孔，加热第一玻璃基板和第二玻璃基板， 控制温度升高，通过施加压力来接合第一玻璃基板和第二玻璃基板以形成接合基板，其中金属图案嵌入在接合基板内，以受控的温度下降冷却接合基板，然后保持接合基板 在适于蚀刻的温度下蚀刻所述键合衬底内的所述金属图案，其中所述蚀刻剂经由所述孔进入所述金属图案，在所述键合衬底内形成空隙，其中所述空隙包括微特征。

公开(公告)号：US08423153B2

公开(公告)日：2013-04-16

申请号：US12296519

申请日：2007-01-26

Applicant: Hans-Jurgen Tiedtke

Inventor： Hans-Jurgen Tiedtke

IPC: A61N1/04

CPC classification number: A61N1/05 ,  A61N1/0543 ,  A61N1/0551 ,  B81C99/008 ,  B81C2201/0107 ,  B81C2201/0181 ,  Y10T428/12493

Abstract: The object, to create a method for producing multilayers or multilayer systems wherein the structures generated on a substrate can easily be jointly detached from the substrate and are preserved in a composite, is achieved by the present invention by means of a method for producing implant structures comprising generating a first metal layer on a substrate, generating a second metal layer above the first metal layer, producing a number of multilayered implant structures above the second metal layer, removing the first metal layer between the substrate and the second metal layer, and releasing the implant structures from the substrate in a coherent composite. With the method according to the invention, between the implant structures and the substrate a release layer is generated consisting of two or three metal layers which serve as sacrificial layer in the course of releasing the fully processed multilayers by means of an under-etching process. As a result, a uniform and reliable separation of the finished multilayers from the substrate in a composite is achieved, facilitating the subsequent technology for assembly and interconnection of the implant structures.

Abstract translation: 本发明的目的是为了产生多层或多层体系的制造方法，其中在衬底上产生的结构可以容易地与衬底共同分离并且被保存在复合材料中，这通过本发明通过生产植入结构的方法来实现 包括在衬底上产生第一金属层，在第一金属层上方产生第二金属层，在第二金属层之上产生多个多层植入结构，去除衬底和第二金属层之间的第一金属层，并释放 在相干复合材料中来自基底的植入物结构。 利用根据本发明的方法，在植入结构和衬底之间，产生剥离层，其由在蚀刻过程中释放完全处理的多层膜的过程中用作牺牲层的两个或三个金属层组成。 结果，实现了在复合材料中完成的多层与基底的均匀可靠的分离，有助于随后的用于植入结构的组装和互连的技术。

公开(公告)号：US08062497B2

公开(公告)日：2011-11-22

申请号：US11729305

申请日：2007-03-28

Applicant: Ann Witvrouw ,  Raquel Hellin Rico ,  Jean-Pierre Celis

Inventor： Ann Witvrouw ,  Raquel Hellin Rico ,  Jean-Pierre Celis

IPC: C25D5/02

CPC classification number: B81C1/00293 ,  B81B2203/0109 ,  B81B2203/0315 ,  B81C2201/0107 ,  B81C2203/0136 ,  B81C2203/0145 ,  Y10T428/249953

Abstract: One inventive aspect relates to a method for forming hermetically sealed cavities, e.g. semiconductor cavities comprising fragile devices, MEMS or NEMS devices. The method allows forming hermetically sealed cavities at a controlled atmosphere and pressure and at low temperatures, for example, at temperatures not exceeding about 200° C. The method further allows forming sealed cavities with short release times, for example, release times of about a few minutes to 30 minutes. The method may, for example, be used for zero level packaging of MEMS or NEMS devices.

Abstract translation: 本发明的一个方面涉及用于形成密封腔的方法，例如， 半导体腔包括易碎器件，MEMS或NEMS器件。 该方法允许在受控的气氛和压力以及在低温下，例如在不超过约200℃的温度下形成气密密封腔。该方法还允许形成具有短释放时间的密封空腔，例如约一 几分钟到30分钟。 该方法可以例如用于MEMS或NEMS装置的零级封装。

公开(公告)号：US07932728B2

公开(公告)日：2011-04-26

申请号：US12485430

申请日：2009-06-16

Applicant: Chen-Jean Chou ,  Chun-chen Wu ,  Patrick F. Brinkley

Inventor： Chen-Jean Chou ,  Chun-chen Wu ,  Patrick F. Brinkley

IPC: G01R31/08

CPC classification number: B81C99/004 ,  B81B2201/047 ,  B81C1/00714 ,  B81C2201/0107 ,  G02B26/001

Abstract: A method of fabricating a MEMS device includes conditioning of an insulating layer by applying a voltage across the insulating layer via a conductive sacrificial layer for a period of time, prior to removal of the conductive sacrificial layer. This conditioning process may be used to saturate or stabilize charge accumulated within the insulating layer. The resistance across the insulating layer may also be measured to detect possible defects in the insulating layer.

Abstract translation: 制造MEMS器件的方法包括通过在去除导电牺牲层之前通过导电牺牲层在绝缘层上施加电压一段时间来调节绝缘层。 该调理过程可用于饱和或稳定在绝缘层内积聚的电荷。 还可以测量绝缘层两端的电阻，以检测绝缘层中的可能缺陷。

公开(公告)号：US20100096714A1

公开(公告)日：2010-04-22

申请号：US12580052

申请日：2009-10-15

Applicant: Goro NAKATANI

Inventor： Goro NAKATANI

IPC: H01L29/84 ,  H01L21/306

CPC classification number: B81B3/001 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81C1/00476 ,  B81C1/00595 ,  B81C2201/0107 ,  G01L9/0042 ,  G01L9/0073 ,  H04R19/005

Abstract: A method of manufacturing an MEMS sensor according to the present invention includes the steps of: forming a first sacrificial layer on one surface of a substrate; forming a lower electrode on the first sacrificial layer; forming a second sacrificial layer made of a metallic material on the first sacrificial layer to cover the lower electrode; forming an upper electrode made of a metallic material on the second sacrificial layer; forming a protective film made of a nonmetallic material on the substrate to collectively cover the first sacrificial layer, the second sacrificial layer and the upper electrode; and removing at least the second sacrificial layer by forming a through-hole in the protective film and supplying an etchant to the inner side of the protective film through the through-hole.

Abstract translation: 根据本发明的MEMS传感器的制造方法包括以下步骤：在衬底的一个表面上形成第一牺牲层; 在所述第一牺牲层上形成下电极; 在所述第一牺牲层上形成由金属材料制成的第二牺牲层以覆盖所述下电极; 在所述第二牺牲层上形成由金属材料制成的上电极; 在所述基板上形成由非金属材料制成的保护膜，以共同覆盖所述第一牺牲层，所述第二牺牲层和所述上电极; 以及通过在所述保护膜中形成通孔并且通过所述通孔向所述保护膜的内侧供给蚀刻剂，至少去除所述第二牺牲层。

公开(公告)号：US07666702B2

公开(公告)日：2010-02-23

申请号：US11946831

申请日：2007-11-28

Applicant: Sheng-Hung Li ,  Siew-Seong Tan ,  Cheng-Yen Liu ,  Li-Ken Yeh

Inventor： Sheng-Hung Li ,  Siew-Seong Tan ,  Cheng-Yen Liu ,  Li-Ken Yeh

IPC: H01L21/00 ,  H01L21/4763 ,  G02B26/00

CPC classification number: B81C1/00801 ,  B81C2201/0107 ,  B81C2201/014

Abstract: A method for fabricating a microstructure is to form at least one insulation layer including a micro-electro-mechanical structure therein over an upper surface of a silicon substrate. The micro-electro-mechanical structure includes at least one microstructure and a metal sacrificial structure that are independent with each other. In the metal sacrificial structure are formed a plurality of metal layers and a plurality of metal via layers connected to the respective metal layers. A barrier layer is formed over an upper surface of the insulation layer, and an etching stop layer is subsequently formed over a lower surface of the silicon substrate. An etching operation is carried out from the lower surface of the silicon substrate to form a space corresponding to the micro-electro-mechanical structure, and then the metal sacrificial structure is etched, thus achieving a microstructure suspension.

Abstract translation: 用于制造微结构的方法是在硅衬底的上表面上形成包括微​​电子机械结构的至少一个绝缘层。 微电子机械结构包括彼此独立的至少一个微结构和金属牺牲结构。 在金属牺牲结构中形成多个金属层和连接到各个金属层的多个金属通孔层。 在绝缘层的上表面上形成阻挡层，随后在硅衬底的下表面上形成蚀刻停止层。 从硅衬底的下表面进行蚀刻操作以形成与微电子机械结构相对应的空间，然后蚀刻金属牺牲结构，从而实现微结构悬浮。

公开(公告)号：US20090315567A1

公开(公告)日：2009-12-24

申请号：US12485430

申请日：2009-06-16

Applicant: Chen-Jean Chou ,  Chun-chen Wu ,  Patrick F. Brinkley

Inventor： Chen-Jean Chou ,  Chun-chen Wu ,  Patrick F. Brinkley

IPC: H01H31/12 ,  G01R27/02

CPC classification number: B81C99/004 ,  B81B2201/047 ,  B81C1/00714 ,  B81C2201/0107 ,  G02B26/001

Abstract: A method of fabricating a MEMS device includes conditioning of an insulating layer by applying a voltage across the insulating layer via a conductive sacrificial layer for a period of time, prior to removal of the conductive sacrificial layer. This conditioning process may be used to saturate or stabilize charge accumulated within the insulating layer. The resistance across the insulating layer may also be measured to detect possible defects in the insulating layer.

Abstract translation: 制造MEMS器件的方法包括通过在去除导电牺牲层之前通过导电牺牲层在绝缘层上施加电压一段时间来调节绝缘层。 该调理过程可用于饱和或稳定在绝缘层内积聚的电荷。 还可以测量绝缘层两端的电阻，以检测绝缘层中的可能缺陷。

公开(公告)号：US20090165295A1

公开(公告)日：2009-07-02

申请号：US12233142

申请日：2008-09-18

Applicant: Adam L. Cohen ,  Gang Zhang ,  Fan-Gang Tseng

Inventor： Adam L. Cohen ,  Gang Zhang ,  Fan-Gang Tseng

IPC: H05K3/00 ,  H05K3/02 ,  H05K3/10 ,  H05K3/22 ,  C25D5/02

CPC classification number: B81C1/00611 ,  B81B2201/042 ,  B81C1/00126 ,  B81C2201/0107 ,  B81C2201/0122 ,  B81C2201/056 ,  G01P15/0802 ,  G01P15/125 ,  H01P1/202 ,  H01P3/06 ,  H01P5/183 ,  H01P11/00 ,  H01P11/005 ,  H01P11/007 ,  H05K3/4647 ,  Y10T29/49155

Abstract: Various embodiments are directed to the electrochemical fabrication of multilayer mesoscale or microscale structures which are formed using at least one conductive structural material, at least one conductive sacrificial material, and at least one dielectric material. In some embodiments the dielectric material is a UV-curable photopolymer. In other embodiments, electrochemically fabricated structures are formed on dielectric substrates.

Abstract translation: 各种实施方案涉及使用至少一种导电结构材料，至少一种导电牺牲材料和至少一种介电材料形成的多层中尺度或微结构结构的电化学制造。 在一些实施方案中，电介质材料是可UV固化的光聚合物。 在其它实施例中，在电介质基底上形成电化学制造的结构。

公开(公告)号：US20090160028A1

公开(公告)日：2009-06-25

申请号：US12248804

申请日：2008-10-09

Applicant: CHENG-RONG YI-LI ,  QUN-QING LI ,  SHOU-SHAN FAN

Inventor： CHENG-RONG YI-LI ,  QUN-QING LI ,  SHOU-SHAN FAN

IPC: H01L23/58 ,  H01L21/306

CPC classification number: B81B3/001 ,  B81C2201/0107

Abstract: An exemplary method for forming gaps in a micromechanical device includes providing a substrate. A first material layer is deposited over the substrate. A sacrificial layer is deposited over the first material layer. A second material layer is deposited over the sacrificial layer such that at least a portion of the sacrificial layer is exposed. The exposed portion of the sacrificial layer is etched by dry etching. The remaining portion of the sacrificial layer is etched by wet etching to form gaps between the first material layer and the second material layer. One or more bulges are formed at one side of the second material layer facing the first material layer, and are a portion of the sacrificial layer remaining after the wet etching.

Abstract translation: 用于在微机械装置中形成间隙的示例性方法包括提供基底。 第一材料层沉积在衬底上。 在第一材料层上沉积牺牲层。 在牺牲层上沉积第二材料层，使得牺牲层的至少一部分被暴露。 通过干蚀刻来蚀刻牺牲层的暴露部分。 通过湿蚀刻来蚀刻牺牲层的剩余部分，以在第一材料层和第二材料层之间形成间隙。 在第二材料层的面向第一材料层的一侧形成一个或多个凸起，并且是在湿蚀刻之后残留的牺牲层的一部分。

公开(公告)号：US20070298238A1

公开(公告)日：2007-12-27

申请号：US11729305

申请日：2007-03-28

Applicant: Ann Witvrouw ,  Raquel Rico ,  Jean-Pierre Celis

Inventor： Ann Witvrouw ,  Raquel Rico ,  Jean-Pierre Celis

IPC: B32B3/26 ,  B05D5/12 ,  C25D5/10

CPC classification number: B81C1/00293 ,  B81B2203/0109 ,  B81B2203/0315 ,  B81C2201/0107 ,  B81C2203/0136 ,  B81C2203/0145 ,  Y10T428/249953

Abstract: One inventive aspect relates to a method for forming hermetically sealed cavities, e.g. semiconductor cavities comprising fragile devices, MEMS or NEMS devices. The method allows forming hermetically sealed cavities at a controlled atmosphere and pressure and at low temperatures, for example, at temperatures not exceeding about 200° C. The method further allows forming sealed cavities with short release times, for example, release times of about a few minutes to 30 minutes. The method may, for example, be used for zero level packaging of MEMS or NEMS devices.

Abstract translation: 本发明的一个方面涉及用于形成密封腔的方法，例如， 半导体腔包括易碎器件，MEMS或NEMS器件。 该方法允许在受控的气氛和压力以及在低温下，例如在不超过约200℃的温度下形成气密密封腔。该方法还允许形成具有短释放时间的密封空腔，例如约一 几分钟到30分钟。 该方法可以例如用于MEMS或NEMS装置的零级封装。