公开(公告)号：US08309998B2

公开(公告)日：2012-11-13

申请号：US13102039

申请日：2011-05-05

申请人： Tzung-Han Lee ,  Chung-Yuan Lee

发明人： Tzung-Han Lee ,  Chung-Yuan Lee

IPC分类号： H01L27/108

CPC分类号： H01L29/7841 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7827

摘要： A memory structure having a floating body is provided, which includes a substrate including an active area and an isolation structure surrounding the active area, a first source/drain region in the substrate in the active area, a first floating body in the substrate above the first source/drain region, a second floating body on the first floating body, a second source/drain region on the second floating body, and a trench-type gate structure in the substrate and beside the first floating body. A method of fabricating a memory structure having a floating body is also provided.

摘要翻译： 提供一种具有浮体的存储器结构，其包括：衬底，其包括有源区域和围绕有源区域的隔离结构;有源区域中的衬底中的第一源极/漏极区域;位于衬底中的第一浮置体 第一源极/漏极区域，第一浮体上的第二浮体，第二浮体上的第二源极/漏极区域，以及衬底中的沟槽型栅极结构以及第一浮体旁边。 还提供了一种制造具有浮体的存储结构的方法。

公开(公告)号：US20110226736A1

公开(公告)日：2011-09-22

申请号：US13118604

申请日：2011-05-31

申请人： Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng ,  Chung-Yuan Lee ,  Shian-Jyh Lin

发明人： Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng ,  Chung-Yuan Lee ,  Shian-Jyh Lin

IPC分类号： C23F1/02 ,  C23F1/26

CPC分类号： C23F1/26 ,  H01L21/32134

摘要： A method of patterning a metal alloy material layer having hafnium and molybdenum. The method includes forming a patterned mask layer on a metal alloy material layer having hafnium and molybdenum on a substrate. The patterned mask layer is used as a mask and an etching process is performed using an etchant on the metal alloy material layer having hafnium and molybdenum so as to form a metal alloy layer having hafnium and molybdenum. The etchant includes at least nitric acid, hydrofluoric acid and sulfuric acid. The patterned mask layer is removed.

摘要翻译： 图案化具有铪和钼的金属合金材料层的方法。 该方法包括在基板上的具有铪和钼的金属合金材料层上形成图案化掩模层。 图案化掩模层用作掩模，并且使用具有铪和钼的金属合金材料层上的蚀刻剂进行蚀刻处理，以形成具有铪和钼的金属合金层。 蚀刻剂至少包括硝酸，氢氟酸和硫酸。 去除图案化的掩模层。

公开(公告)号：US20110156285A1

公开(公告)日：2011-06-30

申请号：US12758289

申请日：2010-04-12

申请人： YUAN KU LAN ,  CHUNG-YUAN LEE

发明人： YUAN KU LAN ,  CHUNG-YUAN LEE

IPC分类号： H01L23/544 ,  H01L21/66

CPC分类号： G03F7/70633 ,  G03F9/7076

摘要： An integrated alignment and overlay mark for detecting the exposed errors of the photolithography process between a pre-layer and a current layer is disclosed. The integrated alignment and overlay mark includes an alignment mark and an overlay mark in the same shot region. The alignment mark is formed surrounding the overlay mark; therefore, the gap or the orientation between the pre-layer and the current layer can be calculated in order to check the alignment accuracy of photolithography process.

摘要翻译： 公开了用于检测预层和当前层之间的光刻工艺的暴露误差的集成对准和覆盖标记。 集成对齐和重叠标记包括在相同拍摄区域中的对准标记和重叠标记。 对准标记形成在覆盖标记周围; 因此，为了检查光刻工艺的对准精度，可以计算预层和当前层之间的间隙或取向。

公开(公告)号：US07633109B2

公开(公告)日：2009-12-15

申请号：US11965769

申请日：2007-12-28

申请人： Tzung-Han Lee ,  Chih-Hao Cheng ,  Te-Yin Chen ,  Chung-Yuan Lee ,  En-Jui Li

发明人： Tzung-Han Lee ,  Chih-Hao Cheng ,  Te-Yin Chen ,  Chung-Yuan Lee ,  En-Jui Li

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L29/66621 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L29/4236

摘要： A DRAM structure has a substrate, a buried transistor with a fin structure, a trench capacitor, and a surface strap on the surface of the substrate. The surface strap is used to electrically connect a drain region to the trench capacitor.

摘要翻译： DRAM结构具有衬底，具有翅片结构的埋入晶体管，沟槽电容器和衬底表面上的表面带。 表面带用于将漏极区域电连接到沟槽电容器。

公开(公告)号：US20090134442A1

公开(公告)日：2009-05-28

申请号：US12103590

申请日：2008-04-15

申请人： Shian-Jyh Lin ,  Yuan Tsung Chang ,  Shun-Fu Chen ,  Chung-Tze Lin ,  Chung-Yuan Lee ,  Tse Chuan Kuo

发明人： Shian-Jyh Lin ,  Yuan Tsung Chang ,  Shun-Fu Chen ,  Chung-Tze Lin ,  Chung-Yuan Lee ,  Tse Chuan Kuo

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L29/66621 ,  H01L27/10867 ,  H01L27/10876

摘要： A method for forming a recessed channel device includes providing a substrate with a plurality of trench capacitors formed therein, each of the trench capacitors including a plug protruding above the substrate; forming a spacer on each of the plugs; forming a plurality of trench isolations along a first direction in the substrate adjacent to the trench capacitors so as to define an active area exposing the substrate; removing a portion of the substrate by using the spacers and the trench isolations as a mask to form a recessed channel; and trimming the recessed channel so that a surface profile of the recessed channel presents a three-dimensional shape. A recessed channel device with a rounded channel profile is also provided.

摘要翻译： 用于形成凹陷通道器件的方法包括：提供其上形成有多个沟槽电容器的衬底，每个沟槽电容器包括突出在衬底上方的插头; 在每个插头上形成间隔件; 在与所述沟槽电容器相邻的所述衬底中沿着第一方向形成多个沟槽隔离，以限定暴露所述衬底的有源区; 通过使用间隔物和沟槽隔离物作为掩模去除衬底的一部分以形成凹陷沟道; 并且修整凹陷通道，使得凹陷通道的表面轮廓呈现三维形状。 还提供了具有圆形通道轮廓的凹槽通道装置。

公开(公告)号：US20080009112A1

公开(公告)日：2008-01-10

申请号：US11858703

申请日：2007-09-20

申请人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

发明人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

IPC分类号： H01L21/8242

CPC分类号： H01L29/66621 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10876

摘要： A method for forming a semiconductor memory device with a recessed gate is disclosed. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor is formed in each trench. A protrusion is formed on each deep trench capacitor, wherein a top surface level of each protrusion is higher than that of the pad layer. Spacers are formed on sidewalls of the protrusions, and the pad layer and the substrate are etched using the spacers and the protrusions as a mask to form a recess. A recessed gate is formed in the recess.

摘要翻译： 公开了一种用于形成具有凹入栅极的半导体存储器件的方法。 提供其上具有垫层的衬底。 图案化衬垫层和衬底以形成至少两个沟槽。 在每个沟槽中形成深沟槽电容器。 在每个深沟槽电容器上形成突起，其中每个突起的顶表面水平高于焊盘层的顶表面高度。 间隔件形成在突起的侧壁上，并且使用间隔件和突起作为掩模来蚀刻衬垫层和衬底以形成凹部。 在凹部中形成凹槽。

公开(公告)号：US20050208727A1

公开(公告)日：2005-09-22

申请号：US10871619

申请日：2004-06-18

申请人： Shian-Jyh Lin ,  Yu-Sheng Hsu ,  Chung-Yuan Lee

发明人： Shian-Jyh Lin ,  Yu-Sheng Hsu ,  Chung-Yuan Lee

IPC分类号： H01L21/033 ,  H01L21/20 ,  H01L21/308 ,  H01L21/311 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

CPC分类号： H01L27/1087 ,  H01L21/0337 ,  H01L21/3086 ,  H01L29/66181 ,  H01L29/945

摘要： A method for forming a bottle trench. First, a substrate covered by a photoresist layer is rotated to a specific angle prior to performance of lithography, thereby forming a rectangular opening in the photoresist layer and exposing the substrate, in which edges of the rectangular opening are substantially parallel to the {110} plane of the substrate due to the rotation of the substrate. Next, the exposed substrate is etched to form a trench therein, in which the sidewall surface of the trench is the {110} plane of the substrate. Finally, isotropic etching is performed on the substrate of the lower portion of the trench using an etching shield layer formed on the sidewall of the upper portion of the trench as an etching mask, to form the bottle trench. The invention also discloses a method of fabricating a bottle trench capacitor.

公开(公告)号：US06818547B2

公开(公告)日：2004-11-16

申请号：US10229734

申请日：2002-08-27

申请人： Meng-Hung Chen ,  Yu-Sheng Shu ,  Ming Hung Lo ,  Chung-Yuan Lee

发明人： Meng-Hung Chen ,  Yu-Sheng Shu ,  Ming Hung Lo ,  Chung-Yuan Lee

IPC分类号： H01L214763

CPC分类号： H01L21/76844 ,  H01L21/76808 ,  H01L21/76877

摘要： A dual damascene process for producing interconnects. A dielectric layer is formed over the surface of a semiconductor substrate which comprises conductive layers or MOS devices. The dielectric layer is patterned to form trench openings and a metal layer is deposited over the dielectric layer to fill the plurality of trenches. A photoresist layer is formed over the metal layer and defined to form via hole patterns above the trenches. The metal layer and the dielectric layer are etched with the patterned photoresist layer as a mask to form a plurality of via holes exposing the underlying conductive layer or MOS devices and a dual damascene opening is formed.

摘要翻译： 用于生产互连的双镶嵌工艺。 在包括导电层或MOS器件的半导体衬底的表面上形成电介质层。 图案化电介质层以形成沟槽开口，并且在电介质层上沉积金属层以填充多个沟槽。 光致抗蚀剂层形成在金属层之上，并被限定为在沟槽上形成通孔图案。 用图案化的光致抗蚀剂层作为掩模蚀刻金属层和电介质层，以形成暴露下面的导电层或MOS器件的多个通孔，并形成双镶嵌开口。

公开(公告)号：US5998832A

公开(公告)日：1999-12-07

申请号：US955872

申请日：1997-10-22

申请人： Shing-Ren Sheu ,  Chung-Yuan Lee

发明人： Shing-Ren Sheu ,  Chung-Yuan Lee

IPC分类号： H01L21/336 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L29/66568 ,  H01L27/0251 ,  H01L27/0266

摘要： An improved metal oxide field effect transistor (MOSFET) provides an electro-static protection device with a high resistance to electro-static discharge. The electro-static discharge protection device has pre-gate heavily doped regions adjacent to the source and drain regions, where the pre-gate regions extend at least partially under the gate electrode. A single heavily doped pre-gate region may be provided for the MOSFET of the electro-static discharge protection circuit.

摘要翻译： 改进的金属氧化物场效应晶体管（MOSFET）提供了具有高静电放电电阻的静电保护装置。 静电放电保护器件具有与源极和漏极区域相邻的预栅极重掺杂区域，其中预栅极区域至少部分地延伸到栅电极下方。 可以为静电放电保护电路的MOSFET提供单个重掺杂的预栅极区域。

公开(公告)号：US5473169A

公开(公告)日：1995-12-05

申请号：US406170

申请日：1995-03-17

申请人： Ming-Dou Ker ,  Chung-Yu Wu ,  Chung-Yuan Lee ,  Joe Ko

发明人： Ming-Dou Ker ,  Chung-Yu Wu ,  Chung-Yuan Lee ,  Joe Ko

IPC分类号： H01L27/02 ,  H01L29/74 ,  H01L29/06

CPC分类号： H01L27/0259

摘要： A complementary-SCR electrostatic discharge protection circuit in a silicon substrate, coupling to I/O pads for bypassing electrostatic current of positive or negative polarity respect to power supply voltages V.sub.DD and V.sub.SS. The circuit comprises a first SCR and a second SCR each having an anode, a cathode, an anode gate and a cathode gate. The circuit of the present invention preferably includes a finger type layout structure for providing a larger capacity to bypass electrostatic current. It is also characterized by a base-emitter shorting design to avoid a V.sub.DD -to-V.sub.SS latch-up effect.

摘要翻译： 在硅衬底中的互补SCR静电放电保护电路，耦合到I / O焊盘，用于绕过电源电压VDD和VSS旁路正极或负极性的静电电流。 电路包括第一SCR和第二SCR，每个具有阳极，阴极，阳极栅极和阴极栅极。 本发明的电路优选地包括用于提供更大容量来绕过静电电流的手指型布局结构。 它还具有基极 - 发射极短路设计的特征，以避免VDD至VSS闭锁效应。