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9 条记录 (耗时 0.013 秒)

    Hybrid ASIC/memory module package
    3.
    发明授权
    Hybrid ASIC/memory module package 有权
    混合ASIC /内存模块封装

    公开(公告)号：US6137174A

    公开(公告)日：2000-10-24

    申请号：US318943

    申请日：1999-05-26

    申请人： Kuo-Ning Chiang ,  Wen-Hwa Chen ,  Kuo-Tai Tseng

    发明人： Kuo-Ning Chiang ,  Wen-Hwa Chen ,  Kuo-Tai Tseng

    IPC分类号： H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/3735 ,  H01L23/3128 ,  H01L23/4334 ,  H01L2224/16 ,  H01L2924/1433

    摘要： A package for multiple IC chip module. The IC chip is attached to electric wires on ceramic substrate which has good heat dissipating capability. The bonding pads along the periphery of the ceramic substrate are lead-bonded to a second substrate with printed wiring on at least one side of the surfaces and ball grid array at the bottom surface. Double-sided printed wiring can be used to provide multiple-layered interconnection. The IC chip is separated from the second substrate by a resin to cushion the stress due to difference in thermal expansion coefficients of the IC chip and the second substrate.

    摘要翻译： 一个封装，用于多个IC芯片模块。 IC芯片附着在具有良好散热能力的陶瓷基板上的电线上。 沿着陶瓷基板的周边的接合焊盘在表面的至少一侧上的引线接合到具有印刷布线的第二基板，并且在底表面处具有球栅阵列。 双面印刷布线可用于提供多层互连。 IC芯片通过树脂与第二基板分离，以缓冲由于IC芯片和第二基板的热膨胀系数的差异引起的应力。

    Glueless integrated circuit system in a packaging module
    6.
    发明授权
    Glueless integrated circuit system in a packaging module 有权
    封装模块中的无胶集成电路系统

    公开(公告)号：US06781225B2

    公开(公告)日：2004-08-24

    申请号：US10310366

    申请日：2002-12-06

    申请人： Kuo-Ning Chiang ,  Wen-Hwa Chen ,  Kuo-Tai Tseng

    发明人： Kuo-Ning Chiang ,  Wen-Hwa Chen ,  Kuo-Tai Tseng

    IPC分类号： H01L2302

    CPC分类号： H01L23/49816 ,  H01L23/49833 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/09701 ,  H01L2924/00014

    摘要： An integrated circuit chip with ball-grid array solder balls is packaged as a module without being sealed in protective glue. The IC chip is mounted on an insulating substrate with pads to support the solder balls. The pads are connected to a second set of pads along the periphery of the substrate. Leads are pressed against the second set of pads for external connections. A second IC chip may be pressed against the other side of the substrate to increase the external connections.

    摘要翻译： 具有球栅阵列焊球的集成电路芯片作为模块封装，不用密封在保护胶中。 IC芯片安装在具有焊盘的绝缘基板上以支撑焊球。 焊盘沿着衬底的周边连接到第二组焊盘。 引线被压在第二组焊盘上用于外部连接。 可以将第二IC芯片压靠在基板的另一侧以增加外部连接。

    Stacked multiple-chip module micro ball grid array packaging
    7.
    发明授权
    Stacked multiple-chip module micro ball grid array packaging 有权
    堆叠多芯片模块微球格栅阵列封装

    公开(公告)号：US6023097A

    公开(公告)日：2000-02-08

    申请号：US271214

    申请日：1999-03-17

    申请人： Kuo-Ning Chiang ,  Wen-Hwa Chen ,  Kuo-Tai Tseng

    发明人： Kuo-Ning Chiang ,  Wen-Hwa Chen ,  Kuo-Tai Tseng

    IPC分类号： H01L23/16 ,  H01L23/31 ,  H01L25/065 ,  H01L23/12

    CPC分类号： H01L23/16 ,  H01L23/3107 ,  H01L25/0655 ,  H01L2224/05599 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/85399 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/14

    摘要： A micro ball grid array package is devised for a multiple-chip module (MCM). The IC chips in the package are stacked to save space. The bonding pads for the lower IC chip or chips are placed along the edges where the pads are not masked by the stacking of the upper chip or chips. When there are more than one chip at each level of the stacking, the IC chips at each level are butted with each other to further save space. The bonding pads of the chips are wire-bonded to a printed wiring plate, which has via holes through the printed wiring plate for connection to the ball grid array at the other side of the printed wiring plate and for surface mounting to a printed circuit board. A heat dissipating plate may be inserted at the bottom of the IC chips away from the stacking surface.

    摘要翻译： 针对多芯片模块（MCM）设计了一种微型球栅阵列封装。 堆叠中的IC芯片堆叠以节省空间。 用于下部IC芯片或芯片的接合焊盘沿着不被上部芯片或芯片堆叠而不掩盖焊盘的边缘放置。 当堆叠的每个级别有多个芯片时，各级的IC芯片相互对接，以进一步节省空间。 芯片的接合焊盘被引线接合到印刷布线板，印刷布线板具有穿过印刷布线板的通孔，用于连接到印刷布线板的另一侧的球栅阵列，并且用于表面安装到印刷电路板 。 散热板可以在IC芯片的底部插入远离堆叠表面。

    Silicon pressure micro-sensing device and the fabrication process
    9.
    发明授权
    Silicon pressure micro-sensing device and the fabrication process 失效
    硅压敏元件及其制造工艺

    公开(公告)号：US06541834B1

    公开(公告)日：2003-04-01

    申请号：US09975125

    申请日：2001-10-09

    申请人： Jin-shown Shie ,  Ji-cheng Lin ,  Chun-te Lin ,  Chih-tang Peng ,  Shih-han Yu ,  Kuo-ning Chiang

    发明人： Jin-shown Shie ,  Ji-cheng Lin ,  Chun-te Lin ,  Chih-tang Peng ,  Shih-han Yu ,  Kuo-ning Chiang

    IPC分类号： H01L2982

    CPC分类号： B81C1/00182 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/014 ,  B81C2201/016 ,  G01L9/0054

    摘要： The invention is a silicon pressure micro-sensing device and the fabrication process thereof. The silicon pressure micro-sensing device includes a pressure chamber, and is constituted of a P-type substrate with a taper chamber and an N-type epitaxial layer thereon. On the N-type epitaxial layer are a plurality of piezo-resistance sensing units which sense deformation caused by pressure. The fabrication pressure of the silicon pressure micro-sensing device includes a step of first making a plurality of holes on the N-type epitaxial layer to reach the P-type substrate beneath. Then, by an anisotropic etching stop technique, in which etchant pass through the holes, a taper chamber is formed in the P-type substrate. Finally, an insulating material is applied to seal the holes, thus attaining the silicon pressure micro-sensing device that is able to sense pressure differences between two ends thereof.

    摘要翻译： 本发明是一种硅压力微型感测装置及其制造方法。 硅压力微型感测装置包括压力室，由具有锥形室的P型衬底和其上的N型外延层构成。 在N型外延层上是感测由压力引起的变形的多个压电感测单元。 硅压力微型感测装置的制造压力包括首先在N型外延层上制造多个孔以到达下面的P型衬底的步骤。 然后，通过各向异性蚀刻停止技术，其中蚀刻剂穿过孔，在P型衬底中形成锥形室。 最后，施加绝缘材料以密封孔，从而获得能够感测其两端之间的压力差的硅压力微检测装置。