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    METHOD FOR DIE BONDING HAVING PICK-AND-PROBING FEATURE
    2.
    发明申请
    METHOD FOR DIE BONDING HAVING PICK-AND-PROBING FEATURE 审中-公开
    具有拾音和探测特征的DIE接合方法

    公开(公告)号：US20090227048A1

    公开(公告)日：2009-09-10

    申请号：US12042093

    申请日：2008-03-04

    申请人： Li-Chih FANG ,  Wen-Jeng Fan ,  Nan-Chun Lin

    发明人： Li-Chih FANG ,  Wen-Jeng Fan ,  Nan-Chun Lin

    IPC分类号： H01L21/66

    CPC分类号： H01L21/67144 ,  H01L21/67271

    摘要： Disclosed is a die-bonding method having pick-and-probe features after wafer sawing where at least a die is probed and sorted according to different grades during a pick-and-place step performed after wafer sawing. A suction nozzle having a plurality of probes is utilized to probe the electrical terminals of the die. After picking, the suction nozzle is moved on a common moving path and the picked die is tested through the suction nozzle. The picked-and-probed die is moved and die-bonded to a die carrier loaded in a corresponding one of a plurality of die-bonding areas by moving the Suction nozzle on a chosen sorting path. Therefore, the die is probed and sorted during die-bonding processes. Higher graded dice at a same level are assembled on a same die carrier to form a higher graded semiconductor package.

    摘要翻译： 公开了一种在晶片锯切之后具有拾取和探针特征的芯片接合方法，其中在晶片锯切之后执行的拾取和放置步骤期间，至少一个模具被探测并根据不同的等级进行分类。 使用具有多个探针的吸嘴来探测管芯的电端子。 拾取后，吸嘴在公共移动路径上移动，并通过吸嘴测试拾取的模具。 通过在所选择的分选路径上移动吸入喷嘴，将拾取和探测的模具移动并压模到装载在多个芯片接合区域中的相应的一个芯片接合区域中的模具载体。 因此，在芯片接合工艺期间探针和分选。 相同级别的较高分级骰子组装在相同的裸片载体上以形成更高级别的半导体封装。

    IC chip package with near substrate scale chip attachment
    3.
    发明申请
    IC chip package with near substrate scale chip attachment 审中-公开
    IC芯片封装附近具有基板尺寸芯片附件

    公开(公告)号：US20080169551A1

    公开(公告)日：2008-07-17

    申请号：US11653422

    申请日：2007-01-16

    申请人： Wen-Jeng Fan ,  Li-Chih Fang

    发明人： Wen-Jeng Fan ,  Li-Chih Fang

    IPC分类号： H01L23/13

    CPC分类号： H01L23/13 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： An IC package with a near-substrate-scale die-attaching layer includes a substrate, a near-substrate-scale die-attaching layer, a chip, a plurality of bonding wires, an encapsulant, and a plurality of solder balls. A plurality of ball pads are formed on the bottom surface of the substrate for solder ball placement. The near-substrate-scale die-attaching layer is formed on the top surface of the substrate covering most of the top surface above the ball pads without extending to the edges of the top surface. The active surface of the chip is attached to a first portion of the near-substrate-scale die-attaching layer and is electrically connected to the substrate by the bonding wires. The encapsulant is formed above the top surface of the substrate to cover a second portion of the near-substrate-scale die-attaching layer extending between the substrate and the encapsulant. Therefore, without adding extra components, the intense thermal stresses imposed on some specific solder balls at the corners of the bottom surface of the substrate or under the edges of the chip will be reduced. During on-board TCT, the solder balls will not easily be broken so that the reliability of IC package is enhanced. Moreover, the near-substrate-scale die-attaching layer is completely encapsulated by the encapsulant 250 to have a better resistance to moisture.

    摘要翻译： 具有近基板尺寸的芯片安装层的IC封装包括基板，近基板尺寸的芯片安装层，芯片，多个接合线，密封剂和多个焊球。 在用于焊球放置的基板的底面上形成有多个球垫。 接近基板的模具附接层形成在衬底的顶表面上，该顶表面覆盖球垫上方的大部分顶表面，而不延伸到顶表面的边缘。 芯片的有源表面附着在近基板尺寸的芯片安装层的第一部分上，并通过接合线与基板电连接。 密封剂形成在衬底的顶表面之上，以覆盖在衬底和密封剂之间延伸的接近衬底的管芯附着层的第二部分。 因此，在不增加额外的部件的情况下，施加在基板底面的拐角处或芯片边缘下方的一些特定焊球的强烈的热应力将会降低。 在板载TCT期间，焊球不容易断裂，从而提高了IC封装的可靠性。 此外，近基板尺寸的管芯附着层被密封剂250完全包封以具有更好的耐湿性。

    Ball grid array package structure
    4.
    发明申请
    Ball grid array package structure 审中-公开
    球栅阵列封装结构

    公开(公告)号：US20080099890A1

    公开(公告)日：2008-05-01

    申请号：US11589155

    申请日：2006-10-30

    申请人： Cheng-Pin Chen ,  Wen-Jeng Fan ,  Li-chih Fang

    发明人： Cheng-Pin Chen ,  Wen-Jeng Fan ,  Li-chih Fang

    IPC分类号： H01L23/495

    CPC分类号： H01L23/3128 ,  H01L23/49816 ,  H01L24/97 ,  H01L25/0655 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/18301 ,  H01L2924/00

    摘要： A ball grid array package structure includes: a substrate having at least one chip bearing area on its upper surface and a plurality of electrical-connecting points on its lower surface; a plurality of chips are arranged on the chip bearing area and electrically connected with those electrical-connecting points; a plurality of through holes penetrating the substrate at the edge of chip bearing area; an encapsulant used to cover those chip and filling those through holes to form a strengthened bump surrounding the chip bearing area on the lower surface of the substrate; and a plurality of conductive balls are respectively arranged on those electrical-connecting points. The present invention utilizes the strengthened bump on the bottom of the substrate to enhance the structure strength of the substrate so as to avoid the warpage of the substrate caused from the stress due to the temperature variation during the package process to affect the following processes.

    摘要翻译： 球栅阵列封装结构包括：在其上表面上具有至少一个芯片支承区域的基板和其下表面上的多个电连接点; 多个芯片布置在芯片支承区域上并与那些电连接点电连接; 在芯片承载区域的边缘处穿过基板的多个通孔; 用于覆盖那些芯片并填充这些芯片的密封剂，以形成围绕衬底的下表面上的芯片支承区域的加强凸块; 并且在这些电连接点上分别布置有多个导电球。 本发明利用基板底部的加强凸块来增强基板的结构强度，以避免由于包装过程中的温度变化而引起的应力引起的基板翘曲影响以下工艺。

    Structure of semiconductor substrate and molding method
    5.
    发明申请
    Structure of semiconductor substrate and molding method 审中-公开
    半导体基板的结构和成型方法

    公开(公告)号：US20070278692A1

    公开(公告)日：2007-12-06

    申请号：US11444480

    申请日：2006-06-01

    申请人： Chi-Jang Lo ,  Li-chih Fang

    发明人： Chi-Jang Lo ,  Li-chih Fang

    IPC分类号： H01L23/48

    CPC分类号： H01L21/565 ,  H01L23/13 ,  H01L23/3128 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A chip molded onto a substrate with a slot forms a molded semiconductor structure, wherein the chip covers one end of the slot and the other open. This special design leads the mold flow and enhances the semiconductor by a transverse pressure induced by the molding flow as the semiconductor is being molded. Moreover, to arrange the molded semiconductor structures especially in a cavity formed by the top portion die and bottom mold die avoids the flow spill. The special molded semiconductor structure and arrangement enhance the adhesion onto the bottom mold die to upgrade the molding quality.

    摘要翻译： 模制在具有槽的基板上的芯片形成模制半导体结构，其中芯片覆盖槽的一端而另一端开口。 这种特殊的设计引导模具流动，并且通过在模制半导体时由模制流引起的横向压力来增强半导体。 此外，为了将模制的半导体结构特别设置在由顶部模具和底模具模具形成的空腔中，避免了溢流。 特殊的模制半导体结构和布置增强了对底模具的粘附力，从而提高了成型质量。

    CIRCUIT SUBSTRATE WITH STRONG ADHESION
    9.
    发明申请
    CIRCUIT SUBSTRATE WITH STRONG ADHESION 审中-公开
    具有强粘性的电路基板

    公开(公告)号：US20070298225A1

    公开(公告)日：2007-12-27

    申请号：US11535946

    申请日：2006-09-27

    申请人： Chi-Jang Lo ,  Li-Chih Fang

    发明人： Chi-Jang Lo ,  Li-Chih Fang

    IPC分类号： B32B9/04

    CPC分类号： H05K3/305 ,  H01L23/498 ,  H01L23/49894 ,  H01L2924/0002 ,  Y02P70/613 ,  Y10T428/24802 ,  Y10T428/28 ,  Y10T428/31504 ,  H01L2924/00

    摘要： The surface of the circuit substrate is a solder mask. The solder mask protects the electrical circuit on the circuit substrate against suffering from the environmental damage. By dividing the area of the circuit substrate into the solder mask area and the adhesive area, a bismaleimide triazine layer is formed on the surface of the circuit substrate to coarsen the adhesive area and so as to enhance the adhesion strength between the chip and the circuit substrate.

    摘要翻译： 电路基板的表面是焊接掩模。 焊接掩模保护电路基板上的电路免受环境破坏。 通过将电路基板的面积划分为焊料掩模区域和粘合剂区域，在电路基板的表面上形成双马来酰亚胺三嗪层，以使粘合剂区域粗化，以增强芯片和电路之间的粘合强度 基质。

    Package structure to reduce warpage
    10.
    发明申请
    Package structure to reduce warpage 审中-公开
    包装结构减少翘曲

    公开(公告)号：US20070257345A1

    公开(公告)日：2007-11-08

    申请号：US11508829

    申请日：2006-08-24

    申请人： Wen-Jeng Fan ,  Cheng-Pin Chen ,  Li-chih Fang

    发明人： Wen-Jeng Fan ,  Cheng-Pin Chen ,  Li-chih Fang

    IPC分类号： H01L23/02

    CPC分类号： H01L23/562 ,  H01L21/561 ,  H01L23/3121 ,  H01L24/97 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

    摘要： A package structure includes: a substrate having a chip-bearing area arranged thereon; an window type assistant element arranged on the substrate and surrounding the edge of the chip-bearing area; a plurality of chips arranged within the chip-bearing area; and a package encapsulation covering chips within the chip-bearing area. It can resist the deformation and reduce the damage from the warpage and simultaneously enhance the yield and stability of the package structure.

    摘要翻译： 包装结构包括：其上布置有芯片承载区域的基板; 窗口型辅助元件，布置在基板上并围绕芯片承载区域的边缘; 布置在所述芯片承载区域内的多个芯片; 以及在芯片承载区域内覆盖芯片的封装封装。 可以抵抗变形，减少翘曲的损伤，同时提高包装结构的产量和稳定性。