公开(公告)号：US20080099890A1

公开(公告)日：2008-05-01

申请号：US11589155

申请日：2006-10-30

申请人： Cheng-Pin Chen ,  Wen-Jeng Fan ,  Li-chih Fang

发明人： Cheng-Pin Chen ,  Wen-Jeng Fan ,  Li-chih Fang

IPC分类号： H01L23/495

CPC分类号： H01L23/3128 ,  H01L23/49816 ,  H01L24/97 ,  H01L25/0655 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/18301 ,  H01L2924/00

摘要： A ball grid array package structure includes: a substrate having at least one chip bearing area on its upper surface and a plurality of electrical-connecting points on its lower surface; a plurality of chips are arranged on the chip bearing area and electrically connected with those electrical-connecting points; a plurality of through holes penetrating the substrate at the edge of chip bearing area; an encapsulant used to cover those chip and filling those through holes to form a strengthened bump surrounding the chip bearing area on the lower surface of the substrate; and a plurality of conductive balls are respectively arranged on those electrical-connecting points. The present invention utilizes the strengthened bump on the bottom of the substrate to enhance the structure strength of the substrate so as to avoid the warpage of the substrate caused from the stress due to the temperature variation during the package process to affect the following processes.

摘要翻译： 球栅阵列封装结构包括：在其上表面上具有至少一个芯片支承区域的基板和其下表面上的多个电连接点; 多个芯片布置在芯片支承区域上并与那些电连接点电连接; 在芯片承载区域的边缘处穿过基板的多个通孔; 用于覆盖那些芯片并填充这些芯片的密封剂，以形成围绕衬底的下表面上的芯片支承区域的加强凸块; 并且在这些电连接点上分别布置有多个导电球。 本发明利用基板底部的加强凸块来增强基板的结构强度，以避免由于包装过程中的温度变化而引起的应力引起的基板翘曲影响以下工艺。

公开(公告)号：US20070257345A1

公开(公告)日：2007-11-08

申请号：US11508829

申请日：2006-08-24

申请人： Wen-Jeng Fan ,  Cheng-Pin Chen ,  Li-chih Fang

发明人： Wen-Jeng Fan ,  Cheng-Pin Chen ,  Li-chih Fang

IPC分类号： H01L23/02

CPC分类号： H01L23/562 ,  H01L21/561 ,  H01L23/3121 ,  H01L24/97 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

摘要： A package structure includes: a substrate having a chip-bearing area arranged thereon; an window type assistant element arranged on the substrate and surrounding the edge of the chip-bearing area; a plurality of chips arranged within the chip-bearing area; and a package encapsulation covering chips within the chip-bearing area. It can resist the deformation and reduce the damage from the warpage and simultaneously enhance the yield and stability of the package structure.

摘要翻译： 包装结构包括：其上布置有芯片承载区域的基板; 窗口型辅助元件，布置在基板上并围绕芯片承载区域的边缘; 布置在所述芯片承载区域内的多个芯片; 以及在芯片承载区域内覆盖芯片的封装封装。 可以抵抗变形，减少翘曲的损伤，同时提高包装结构的产量和稳定性。

公开(公告)号：US20090137069A1

公开(公告)日：2009-05-28

申请号：US11987235

申请日：2007-11-28

申请人： Li-Chih Fang ,  Wen-Jeng Fan

发明人： Li-Chih Fang ,  Wen-Jeng Fan

IPC分类号： H01L21/66

CPC分类号： H01L21/78 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00

摘要： A chip packaging process integrates a burn-in test or a high temperature test to simplify overall packaging and testing process flow. One or more chips are disposed on one or more units of a substrate strip where the substrate strip has a plurality of electrical open sections at the plating lines to electrically isolate the external pads between different units. After electrical connection and encapsulation, a burn-in test is executed at the same time of a post mold curing step, with a high-temperature testing if necessary. Therefore, the chips on the substrate strip has been gone through the burn-in test during the encapsulant is completely cured at the post mold curing step and the burn-in test is finished before the singulation step to reduce the overall testing time.

摘要翻译： 芯片封装过程集成了老化测试或高温测试，以简化整个封装和测试流程。 一个或多个芯片设置在衬底条的一个或多个单元上，其中衬底带在电镀线处具有多个电开路部分，以在不同单元之间电隔离外部焊盘。 在电连接和封装之后，在后模具固化步骤的同时进行老化测试，如果需要进行高温测试。 因此，在模塑固化步骤期间封装剂完全固化之前，衬底条上的芯片已经经过老化测试，并且在分离步骤之前完成老化测试以减少整体测试时间。

公开(公告)号：US20080272489A1

公开(公告)日：2008-11-06

申请号：US11824448

申请日：2007-06-29

申请人： Li-Chih Fang ,  Ronald Iwata ,  Wen-Jeng Fan

发明人： Li-Chih Fang ,  Ronald Iwata ,  Wen-Jeng Fan

IPC分类号： H01L23/485

CPC分类号： H05K3/3452 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H05K2201/099 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor chip substrate with solder pad includes: a core layer and at least one conductive structure formed on the surface of the core layer; an insulation layer with at least one patterned opening covering the conductive structure, wherein the patterned opening has a center portion and a plurality of wing portions on the peripheral edge of the center portion to define the exposed area of the conductive structure as the solder pad. The solder pad with wing will improve the adhesion effect between the solder pad and the solder ball.

摘要翻译： 具有焊盘的半导体芯片基板包括芯层和形成在芯层表面上的至少一个导电结构; 绝缘层，其具有覆盖所述导电结构的至少一个图案化开口，其中所述图案化开口具有在所述中心部分的周边边缘上的中心部分和多个翼部，以限定所述导电结构的暴露区域作为所述焊盘。 具有机翼的焊盘将改善焊盘和焊球之间的粘附效应。

公开(公告)号：US07619305B2

公开(公告)日：2009-11-17

申请号：US11889693

申请日：2007-08-15

申请人： Wen-Jeng Fan ,  Li-Chih Fang ,  Ron Iwata

发明人： Wen-Jeng Fan ,  Li-Chih Fang ,  Ron Iwata

IPC分类号： H01L23/02 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L23/488 ,  H01L23/485

CPC分类号： H05K3/3436 ,  H01L23/13 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/83856 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K2201/0367 ,  H05K2201/0379 ,  Y02P70/613 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked semiconductor device primarily comprises semiconductor packages with a plurality of micro contacts and solder paste to soldering the micro contacts. Each semiconductor package comprises a substrate and a chip disposed on the substrate. The micro contacts of the bottom semiconductor package are a plurality of top bumps located on the upper surface of the substrate. The micro contacts of the top semiconductor package are a plurality of bottom bumps located on the lower surface of the substrate. The bottom bumps are aligned with the top bumps and are electrically connected each other by the solder paste. Therefore, the top bumps and the bottom bumps have the same soldering shapes and dimensions for evenly soldering to avoid breakages of the micro bumps during stacking.

公开(公告)号：US07927919B1

公开(公告)日：2011-04-19

申请号：US12630623

申请日：2009-12-03

申请人： Wen-Jeng Fan ,  Li-Chih Fang ,  Ronald Takao Iwata

发明人： Wen-Jeng Fan ,  Li-Chih Fang ,  Ronald Takao Iwata

IPC分类号： H01L21/00

CPC分类号： H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/525 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/731 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor packaging method without an interposer is revealed. A mother chip is a two-layer structure consisting of a semiconductor layer and an organic layer where a redistribution layer is embedded into the organic layer with a plurality of first terminals and a plurality of second terminals disposed on the redistribution layer and exposed from the organic layer. The mother chip is flip-chip mounted on the substrate. The active surface of the daughter chip is in contact with the organic layer with the bonding pads of the daughter chip bonded to the first terminals. Furthermore, a plurality of electrically connecting components electrically connect the second terminals to the substrate. In the multi-chip stacked package, the interposer can be eliminated with a thinner overall package thickness as well as controlled package warpage.

摘要翻译： 揭示了没有插入器的半导体封装方法。 母芯片是由半导体层和有机层组成的两层结构，其中再分布层被嵌入到有机层中，多个第一端子和多个第二端子设置在再分配层上并从有机层暴露出来 层。 母芯片倒装芯片安装在基板上。 子芯片的有源面与有机层接触，子芯片的接合焊盘与第一端子接合。 此外，多个电连接部件将第二端子电连接到基板。 在多芯片堆叠封装中，可以以更薄的整体封装厚度以及受控的封装翘曲消除中介层。

公开(公告)号：US20090227048A1

公开(公告)日：2009-09-10

申请号：US12042093

申请日：2008-03-04

申请人： Li-Chih FANG ,  Wen-Jeng Fan ,  Nan-Chun Lin

发明人： Li-Chih FANG ,  Wen-Jeng Fan ,  Nan-Chun Lin

IPC分类号： H01L21/66

CPC分类号： H01L21/67144 ,  H01L21/67271

摘要： Disclosed is a die-bonding method having pick-and-probe features after wafer sawing where at least a die is probed and sorted according to different grades during a pick-and-place step performed after wafer sawing. A suction nozzle having a plurality of probes is utilized to probe the electrical terminals of the die. After picking, the suction nozzle is moved on a common moving path and the picked die is tested through the suction nozzle. The picked-and-probed die is moved and die-bonded to a die carrier loaded in a corresponding one of a plurality of die-bonding areas by moving the Suction nozzle on a chosen sorting path. Therefore, the die is probed and sorted during die-bonding processes. Higher graded dice at a same level are assembled on a same die carrier to form a higher graded semiconductor package.

摘要翻译： 公开了一种在晶片锯切之后具有拾取和探针特征的芯片接合方法，其中在晶片锯切之后执行的拾取和放置步骤期间，至少一个模具被探测并根据不同的等级进行分类。 使用具有多个探针的吸嘴来探测管芯的电端子。 拾取后，吸嘴在公共移动路径上移动，并通过吸嘴测试拾取的模具。 通过在所选择的分选路径上移动吸入喷嘴，将拾取和探测的模具移动并压模到装载在多个芯片接合区域中的相应的一个芯片接合区域中的模具载体。 因此，在芯片接合工艺期间探针和分选。 相同级别的较高分级骰子组装在相同的裸片载体上以形成更高级别的半导体封装。

公开(公告)号：US20080169551A1

公开(公告)日：2008-07-17

申请号：US11653422

申请日：2007-01-16

申请人： Wen-Jeng Fan ,  Li-Chih Fang

发明人： Wen-Jeng Fan ,  Li-Chih Fang

IPC分类号： H01L23/13

CPC分类号： H01L23/13 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An IC package with a near-substrate-scale die-attaching layer includes a substrate, a near-substrate-scale die-attaching layer, a chip, a plurality of bonding wires, an encapsulant, and a plurality of solder balls. A plurality of ball pads are formed on the bottom surface of the substrate for solder ball placement. The near-substrate-scale die-attaching layer is formed on the top surface of the substrate covering most of the top surface above the ball pads without extending to the edges of the top surface. The active surface of the chip is attached to a first portion of the near-substrate-scale die-attaching layer and is electrically connected to the substrate by the bonding wires. The encapsulant is formed above the top surface of the substrate to cover a second portion of the near-substrate-scale die-attaching layer extending between the substrate and the encapsulant. Therefore, without adding extra components, the intense thermal stresses imposed on some specific solder balls at the corners of the bottom surface of the substrate or under the edges of the chip will be reduced. During on-board TCT, the solder balls will not easily be broken so that the reliability of IC package is enhanced. Moreover, the near-substrate-scale die-attaching layer is completely encapsulated by the encapsulant 250 to have a better resistance to moisture.

摘要翻译： 具有近基板尺寸的芯片安装层的IC封装包括基板，近基板尺寸的芯片安装层，芯片，多个接合线，密封剂和多个焊球。 在用于焊球放置的基板的底面上形成有多个球垫。 接近基板的模具附接层形成在衬底的顶表面上，该顶表面覆盖球垫上方的大部分顶表面，而不延伸到顶表面的边缘。 芯片的有源表面附着在近基板尺寸的芯片安装层的第一部分上，并通过接合线与基板电连接。 密封剂形成在衬底的顶表面之上，以覆盖在衬底和密封剂之间延伸的接近衬底的管芯附着层的第二部分。 因此，在不增加额外的部件的情况下，施加在基板底面的拐角处或芯片边缘下方的一些特定焊球的强烈的热应力将会降低。 在板载TCT期间，焊球不容易断裂，从而提高了IC封装的可靠性。 此外，近基板尺寸的管芯附着层被密封剂250完全包封以具有更好的耐湿性。

公开(公告)号：US20090045523A1

公开(公告)日：2009-02-19

申请号：US11889693

申请日：2007-08-15

申请人： Wen-Jeng Fan ,  Li-Chih Fang ,  Ron Iwata

发明人： Wen-Jeng Fan ,  Li-Chih Fang ,  Ron Iwata

IPC分类号： H01L23/538

CPC分类号： H05K3/3436 ,  H01L23/13 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/83856 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K2201/0367 ,  H05K2201/0379 ,  Y02P70/613 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked semiconductor device primarily comprises semiconductor packages with a plurality of micro contacts and solder paste to soldering the micro contacts. Each semiconductor package comprises a substrate and a chip disposed on the substrate. The micro contacts of the bottom semiconductor package are a plurality of top bumps located on the upper surface of the substrate. The micro contacts of the top semiconductor package are a plurality of bottom bumps located on the lower surface of the substrate. The bottom bumps are aligned with the top bumps and are electrically connected each other by the solder paste. Therefore, the top bumps and the bottom bumps have the same soldering shapes and dimensions for evenly soldering to avoid breakages of the micro bumps during stacking.

摘要翻译： 叠层半导体器件主要包括具有多个微触点和焊膏以焊接微触点的半导体封装。 每个半导体封装包括衬底和设置在衬底上的芯片。 底部半导体封装的微触点是位于衬底的上表面上的多个顶部凸起。 顶部半导体封装的微触点是位于衬底的下表面上的多个底部凸起。 底部凸块与顶部凸起对准，并通过焊膏彼此电连接。 因此，顶部凸块和底部凸块具有相同的焊接形状和尺寸以便均匀焊接，以避免在堆叠期间微凸块的破损。

公开(公告)号：US20070246814A1

公开(公告)日：2007-10-25

申请号：US11508882

申请日：2006-08-24

申请人： Wen-Jeng Fan ,  Li-chih Fang ,  Ronald Iwata

发明人： Wen-Jeng Fan ,  Li-chih Fang ,  Ronald Iwata

IPC分类号： H01L23/02

CPC分类号： H01L23/13 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A ball grid array structure includes a substrate, wherein a plurality of electric contacts are arranged on its lower surface; a chip arranged on the upper surface of the substrate and electrically connecting with those electric-connecting points; at least a through hole on the substrate and arranged around the edge of the chip; a molding compound covering the chip and filling the through hole to form a window-type bump on the lower surface of the substrate; and a plurality of conductive balls arranged on those electric-connecting points on the substrate. The present invention utilizes the window-type bump to enhance the structure strength of the substrate to effectively decrease the warpage of package in the curing process and to provide a support to prevent the crack of the package from the external force.

摘要翻译： 球栅阵列结构包括基板，其中在其下表面上布置有多个电触头; 芯片，布置在基板的上表面上并与那些电连接点电连接; 至少在所述基板上的通孔并围绕所述芯片的边缘布置; 覆盖芯片并填充通孔以在基板的下表面上形成窗型凸块的模塑料; 以及布置在基板上的这些电连接点上的多个导电球。 本发明利用窗型凸起来提高基体的结构强度，从而有效地减少固化过程中包装的翘曲，并提供一种支撑件，以防止包装件的外部力产生裂缝。