公开(公告)号：US09257408B2

公开(公告)日：2016-02-09

申请号：US14435932

申请日：2012-11-21

Applicant: Takayuki Matsumoto ,  Hirotaka Onishi ,  Masuo Koga

Inventor： Takayuki Matsumoto ,  Hirotaka Onishi ,  Masuo Koga

IPC: H01L21/44 ,  H01L21/50 ,  H01L23/02 ,  H01L23/00 ,  H01L23/60 ,  H01L23/10 ,  H01L23/31 ,  H01L23/373 ,  H01L23/544 ,  H01L23/12 ,  H01L25/18 ,  H01L21/56 ,  H01L25/07 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L24/48 ,  H01L21/56 ,  H01L23/10 ,  H01L23/12 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3735 ,  H01L23/49894 ,  H01L23/5386 ,  H01L23/544 ,  H01L23/60 ,  H01L24/29 ,  H01L24/32 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/07 ,  H01L25/072 ,  H01L25/18 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83132 ,  H01L2224/8513 ,  H01L2224/85132 ,  H01L2224/85801 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/20656 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A soldering portion (4) and a Ni plating mark (5) are simultaneously forming by plating on a wiring pattern (2) of an insulating substrate (1). A semiconductor chip (6) is mounted on the insulating substrate (1). A position of the insulating substrate (1) is recognized by the Ni plating mark (5) and a wire (7) is bonded to the semiconductor chip (6). An electrode (8) is joined to the soldering portion (4) by solder (9). The insulating substrate (1), the semiconductor chip (6), the wire (7), and the electrode (8) are encapsulated in an encapsulation material (13).

Abstract translation: 通过电镀在绝缘基板（1）的布线图案（2）上同时形成焊接部分（4）和镀镍标记（5）。 半导体芯片（6）安装在绝缘基板（1）上。 通过Ni电镀标记（5）识别绝缘基板（1）的位置，并且将线（7）接合到半导体芯片（6）。 电极（8）通过焊料（9）与焊接部分（4）接合。 绝缘基板（1），半导体芯片（6），导线（7）和电极（8）被封装在封装材料（13）中。

公开(公告)号：US08466551B2

公开(公告)日：2013-06-18

申请号：US13187711

申请日：2011-07-21

Applicant: Masuo Koga

Inventor： Masuo Koga

IPC: H01L23/48

CPC classification number: H01L25/072 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2924/00013 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor device includes a main current external electrode for connecting a high-voltage main current electrode of a power semiconductor element to the outside, and a resin case into which the main current external electrode is press fitted. The main current external electrode has a press-fitted fixing portion and a claw fixing portion for fixation to the resin case. The claw fixing portion includes a projection passing through a through hole defined in the resin case, and having a bendable claw portion at its tip end.

Abstract translation: 半导体器件包括用于将功率半导体元件的高电压主电极连接到外部的主电流外部电极以及压入主电流外部电极的树脂壳体。 主电流外部电极具有压配固定部分和用于固定到树脂壳体上的爪固定部分。 爪固定部包括通过限定在树脂壳体中的通孔的突起，其顶端具有可弯曲的爪部。

公开(公告)号：US07554192B2

公开(公告)日：2009-06-30

申请号：US11553235

申请日：2006-10-26

Applicant: Masuo Koga ,  Tetsuo Mizoshiri ,  Yukimasa Hayashida

Inventor： Masuo Koga ,  Tetsuo Mizoshiri ,  Yukimasa Hayashida

IPC: H01L23/34

CPC classification number: H01L23/22 ,  H01L23/053 ,  H01L23/24 ,  H01L23/3735 ,  H01L2224/32225

Abstract: A semiconductor device that includes an insulating substrate having an upper conductor formed on an upper surface thereof and a lower conductor formed on a lower surface of the insulating substrate. The device also includes a semiconductor element mounted on the upper surface of the insulating substrate with an under-element solder therebetween. The device further includes a heat sink whereon the insulating substrate is mounted with an under-substrate solder therebetween. The device additionally includes a silicone gel covering the semiconductor element, the under-element solder, and the upper conductor. In addition, the device includes a filler covering the lower conductor and the under-substrate solder, without covering the semiconductor element, the under-element solder, and the upper conductor, and having a thermal conductivity larger than a thermal conductivity of air and a fluidity higher than a fluidity of the silicone gel.

Abstract translation: 一种半导体器件，包括在其上表面上形成有上导体的绝缘基板和形成在所述绝缘基板的下表面上的下导体。 该装置还包括半导体元件，其安装在绝缘基板的上表面上，其间具有下部元件焊料。 该装置还包括散热器，绝缘基板上安装有底板下焊料。 该装置还包括覆盖半导体元件，下部元件焊料和上导体的硅凝胶。 此外，该器件包括覆盖下导体和底基底焊料的填充物，而不覆盖半导体元件，下元件焊料和上导体，并且具有大于空气的热导率的热导率和 流动性高于硅胶的流动性。

公开(公告)号：US07405448B2

公开(公告)日：2008-07-29

申请号：US11538232

申请日：2006-10-03

Applicant: Masuo Koga ,  Tetsuo Mizoshiri ,  Yukimasa Hayashida

Inventor： Masuo Koga ,  Tetsuo Mizoshiri ,  Yukimasa Hayashida

IPC: H01L23/62 ,  H01L21/00 ,  H05K7/20

CPC classification number: H01L25/162 ,  H01L23/647 ,  H01L25/165 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A first insulating substrate is formed on a heat sink, and a semiconductor element is formed thereon. An insulating resin casing is formed so as to cover the first insulating substrate and the semiconductor element. A second insulating substrate is mounted inside the insulating resin casing apart from the first insulating substrate. On the second insulating substrate, a resistance element that functions as a gate balance resistance is fixed by soldering. The second insulating substrate on which the resistance element was thus mounted was made apart from the first insulating substrate on which the semiconductor element was mounted, and was mounted on the side of the insulating resin casing.

Abstract translation: 在散热器上形成第一绝缘基板，在其上形成半导体元件。 形成绝缘树脂外壳以覆盖第一绝缘基板和半导体元件。 第二绝缘基板安装在绝缘树脂外壳的内部，与第一绝缘基板隔开。 在第二绝缘基板上，通过焊接固定用作栅极平衡电阻的电阻元件。 将安装有电阻元件的第二绝缘基板与安装有半导体元件的第一绝缘基板分开，并且安装在绝缘树脂外壳的一侧。

公开(公告)号：US20130249100A1

公开(公告)日：2013-09-26

申请号：US13531843

申请日：2012-06-25

Applicant: Kazuhiro MORISHITA ,  Masuo KOGA ,  Yukimasa HAYASHIDA

Inventor： Kazuhiro MORISHITA ,  Masuo KOGA ,  Yukimasa HAYASHIDA

IPC: H01L23/48

CPC classification number: H01L23/13 ,  H01L23/24 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3738 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L2224/26175 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00013 ,  H01L2924/10253 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A power semiconductor device module includes: a base plate; an insulating substrate mounted on the base plate; and a diode chip mounted on the insulating substrate, wherein the insulating substrate has an upper surface electrode layer disposed on an upper main surface and a lower surface electrode layer disposed on a lower main surface, the diode chip is joined onto the upper surface electrode layer, the lower surface electrode layer is joined onto the upper main surface of the base plate, and a thermal resistance reducing section that reduces thermal resistance is provided in lower surface electrode layer or the base plate of a portion corresponding to a place immediately below the diode chip.

Abstract translation: 功率半导体器件模块包括：基板; 安装在基板上的绝缘基板; 以及安装在所述绝缘基板上的二极管芯片，其中所述绝缘基板具有设置在上主表面上的上表面电极层和设置在下主表面上的下表面电极层，所述二极管芯片接合到所述上表面电极层 ，下表面电极层被接合到基板的上主表面上，并且在下表面电极层或与二极管正下方的位置相对应的部分的基板上设置降低热阻的热阻降低部分 芯片。

公开(公告)号：US06762937B2

公开(公告)日：2004-07-13

申请号：US10314989

申请日：2002-12-10

Applicant: Nobuyoshi Kimoto ,  Takanobu Yoshida ,  Naoki Yoshimatsu ,  Masuo Koga ,  Dai Nakajima ,  Gourab Majumdar ,  Masakazu Fukada

Inventor： Nobuyoshi Kimoto ,  Takanobu Yoshida ,  Naoki Yoshimatsu ,  Masuo Koga ,  Dai Nakajima ,  Gourab Majumdar ,  Masakazu Fukada

IPC: H05K720

CPC classification number: H02M7/003 ,  H01L23/057 ,  H01L23/50 ,  H01L23/60 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/4811 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A power module includes a substrate with a power semiconductor device mounted thereon, a case having an interior in which the substrate is disposed, a cooling fin having a surface on which the substrate and the case are placed, and a smoothing capacitor disposed on an opposite surface of the cooling fin from the surface on which the substrate is placed, the smoothing capacitor being electrically connected to the power semiconductor device for smoothing a voltage to be externally supplied to the power semiconductor device.

Abstract translation: 功率模块包括其上安装有功率半导体器件的衬底，具有其中设置有衬底的内部的壳体，具有衬底和壳体的表面的冷却翅片以及布置在其上的平滑电容器 所述平滑电容器电连接到所述功率半导体器件，用于使外部提供给所述功率半导体器件的电压平滑。

公开(公告)号：US08569890B2

公开(公告)日：2013-10-29

申请号：US13531843

申请日：2012-06-25

Applicant: Kazuhiro Morishita ,  Masuo Koga ,  Yukimasa Hayashida

Inventor： Kazuhiro Morishita ,  Masuo Koga ,  Yukimasa Hayashida

IPC: H01L23/48

CPC classification number: H01L23/13 ,  H01L23/24 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3738 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L2224/26175 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00013 ,  H01L2924/10253 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A power semiconductor device module includes: a base plate; an insulating substrate mounted on the base plate; and a diode chip mounted on the insulating substrate, wherein the insulating substrate has an upper surface electrode layer disposed on an upper main surface and a lower surface electrode layer disposed on a lower main surface, the diode chip is joined onto the upper surface electrode layer, the lower surface electrode layer is joined onto the upper main surface of the base plate, and a thermal resistance reducing section that reduces thermal resistance is provided in lower surface electrode layer or the base plate of a portion corresponding to a place immediately below the diode chip.

Abstract translation: 功率半导体器件模块包括：基板; 安装在基板上的绝缘基板; 以及安装在所述绝缘基板上的二极管芯片，其中所述绝缘基板具有设置在上主表面上的上表面电极层和设置在下主表面上的下表面电极层，所述二极管芯片接合到所述上表面电极层 ，下表面电极层被接合到基板的上主表面上，并且在下表面电极层或与二极管正下方的位置相对应的部分的基板上设置降低热阻的热阻降低部分 芯片。

公开(公告)号：US20080006932A1

公开(公告)日：2008-01-10

申请号：US11553235

申请日：2006-10-26

Applicant: Masuo KOGA ,  Tetsuo Mizoshiri ,  Yukimasa Hayashida

Inventor： Masuo KOGA ,  Tetsuo Mizoshiri ,  Yukimasa Hayashida

IPC: H01L23/34

CPC classification number: H01L23/22 ,  H01L23/053 ,  H01L23/24 ,  H01L23/3735 ,  H01L2224/32225

Abstract: A semiconductor device according to the present invention has an insulating substrate having an upper conductor formed on the upper surface and a lower conductor formed on the lower surface; a semiconductor element mounted on the insulating substrate with an under-element solder therebetween; a heat sink whereon the insulating substrate is mounted with an under-substrate solder therebetween; a silicone gel covering the semiconductor element, the under-element solder and the upper conductor; and a filler covering the lower conductor and the under-substrate solder, and having a thermal conductivity larger than the thermal conductivity of air and a fluidity higher than the fluidity of the silicone gel.

Abstract translation: 根据本发明的半导体器件具有绝缘基板，其具有形成在上表面上的上导体和形成在下表面上的下导体; 半导体元件，其安装在绝缘基板上，其间具有下部元件焊料; 绝缘基板上安装有底板下焊料的散热器; 覆盖半导体元件的硅凝胶，下部元件焊料和上导体; 以及覆盖下导体和底基底焊料并且具有大于空气热导率的导热性和高于硅凝胶的流动性的流动性的填充物的填充物。

公开(公告)号：US20070284745A1

公开(公告)日：2007-12-13

申请号：US11538232

申请日：2006-10-03

Applicant: Masuo KOGA ,  Tetsuo Mizoshiri ,  Yukimasa Hayashida

Inventor： Masuo KOGA ,  Tetsuo Mizoshiri ,  Yukimasa Hayashida

IPC: H01L23/48

CPC classification number: H01L25/162 ,  H01L23/647 ,  H01L25/165 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A first insulating substrate is formed on a heat sink, and a semiconductor element is formed thereon. An insulating resin casing is formed so as to cover the first insulating substrate and the semiconductor element. A second insulating substrate is mounted inside the insulating resin casing apart from the first insulating substrate. On the second insulating substrate, a resistance element that functions as a gate balance resistance is fixed by soldering. The second insulating substrate on which the resistance element was thus mounted was made apart from the first insulating substrate on which the semiconductor element was mounted, and was mounted on the side of the insulating resin casing.

Abstract translation: 在散热器上形成第一绝缘基板，在其上形成半导体元件。 形成绝缘树脂外壳以覆盖第一绝缘基板和半导体元件。 第二绝缘基板安装在绝缘树脂外壳的内部，与第一绝缘基板隔开。 在第二绝缘基板上，通过焊接固定用作栅极平衡电阻的电阻元件。 将安装有电阻元件的第二绝缘基板与安装有半导体元件的第一绝缘基板分开，并且安装在绝缘树脂外壳的一侧。

公开(公告)号：US06700073B2

公开(公告)日：2004-03-02

申请号：US09970029

申请日：2001-10-04

Applicant: Seiki Hiramatsu ,  Satoshi Yanaura ,  Masuo Koga ,  Hirofumi Fujioka

Inventor： Seiki Hiramatsu ,  Satoshi Yanaura ,  Masuo Koga ,  Hirofumi Fujioka

IPC: H05K100

CPC classification number: H01L23/293 ,  H01L23/24 ,  H01L23/295 ,  H01L24/45 ,  H01L24/48 ,  H01L25/072 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/0102 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/12044 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A silicone resin for sealing a semiconductor chip. A cured silicone resin, which is obtained by curing the silicone resin at a given temperature, has a percent elongation, after fracture, measured at a room temperature, not less than 4% of a penetration number at room temperature. A semiconductor device sealed with the silicone resin, when subjected to a heat cycle or a vibration test, provides resistance to cracking, forming of voids, and interfacial peeling-off. The cured silicone resin may have a penetration number not less than 10 and not more than 80 and a loss elasticity not less than 17% of the storage elasticity. A resin member made of the cured silicone resin and sealing a semiconductor chip may include a filler, such as silica or alumina, having a coefficient of linear thermal expansion lower than that of the cured silicone resin.

Abstract translation: 用于密封半导体芯片的硅树脂。 通过在给定温度下固化硅树脂获得的固化的有机硅树脂在断裂后具有百分比的伸长率，在室温下测量不小于室温下穿透数的4％。 用硅酮树脂密封的半导体器件，当进行热循环或振动试验时，提供耐开裂，空隙形成和界面剥离的能力。 固化的有机硅树脂的渗透数可以不小于10且不大于80，并且具有不小于储存弹性的17％的损失弹性。 由固化的硅树脂制成并密封半导体芯片的树脂构件可以包括具有比固化的有机硅树脂低的线性热膨胀系数的填料，例如二氧化硅或氧化铝。