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1.发明授权Methods and apparatus of creating airgap in dielectric layers for the reduction of RC delay 有权在电介质层中产生气隙以减少RC延迟的方法和装置公开(公告)号：US07879683B2
公开(公告)日：2011-02-01
申请号：US11869396
申请日：2007-10-09
申请人： Amir Al-Bayati , Alexandros T. Demos , Kang Sub Yim , Mehul Naik , Zhenjiang “David” Cui , Mihaela Balseanu , Meiyee (Maggie Le) Shek , Li-Qun Xia
发明人： Amir Al-Bayati , Alexandros T. Demos , Kang Sub Yim , Mehul Naik , Zhenjiang “David” Cui , Mihaela Balseanu , Meiyee (Maggie Le) Shek , Li-Qun Xia
IPC分类号： H01L21/76
CPC分类号： H01L21/7682 , H01L21/3105 , H01L21/31111 , H01L21/31144 , H01L21/76825 , H01L21/76834 , H01L21/76849 , H01L21/76885
摘要： A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches.
摘要翻译： 一种用于在互连结构的电介质材料中产生气隙的方法和装置。 一个实施例提供了一种用于形成半导体结构的方法，包括在衬底上沉积第一介电层，在第一介电层中形成沟槽，用导电材料填充沟槽，平坦化导电材料以暴露第一介电层， 在导电材料和暴露的第一电介质层上的阻挡膜，在介电阻挡膜上沉积硬掩模层，在介电阻挡膜和硬掩模层中形成图案，以暴露衬底的选定区域，氧化至少一部分 在衬底的选定区域中的第一介电层，去除第一电介质层的氧化部分以在导电材料周围形成反向沟槽，以及在反向沟槽中形成气隙，同时在反向沟槽中沉积第二电介质材料。
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2.发明申请METHODS AND APPARATUS OF CREATING AIRGAP IN DIELECTRIC LAYERS FOR THE REDUCTION OF RC DELAY 有权用于减少RC延迟的电介质层中产生气泡的方法和装置公开(公告)号：US20090093112A1
公开(公告)日：2009-04-09
申请号：US11869396
申请日：2007-10-09
申请人： AMIR AL-BAYATI , Alexandros T. Demos , Kang Sub Yim , Mehul Naik , Zhenjiang 'David' Cui , Mihaela Balseanu , Meiyee (Maggie Le) Shek , Li-Qun Xia
发明人： AMIR AL-BAYATI , Alexandros T. Demos , Kang Sub Yim , Mehul Naik , Zhenjiang 'David' Cui , Mihaela Balseanu , Meiyee (Maggie Le) Shek , Li-Qun Xia
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/3105 , H01L21/31111 , H01L21/31144 , H01L21/76825 , H01L21/76834 , H01L21/76849 , H01L21/76885
摘要： A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches.
摘要翻译： 一种用于在互连结构的电介质材料中产生气隙的方法和装置。 一个实施例提供了一种用于形成半导体结构的方法，包括在衬底上沉积第一介电层，在第一介电层中形成沟槽，用导电材料填充沟槽，平坦化导电材料以暴露第一介电层， 在导电材料和暴露的第一电介质层上的阻挡膜，在介电阻挡膜上沉积硬掩模层，在介电阻挡膜和硬掩模层中形成图案，以暴露衬底的选定区域，氧化至少一部分 在衬底的选定区域中的第一介电层，去除第一电介质层的氧化部分以在导电材料周围形成反向沟槽，以及在反向沟槽中形成气隙，同时在反向沟槽中沉积第二电介质材料。
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公开(公告)号：US20090087977A1
公开(公告)日：2009-04-02
申请号：US12241826
申请日：2008-09-30
IPC分类号： H01L21/3205
CPC分类号： H01L21/31608 , C23C16/0272 , H01L21/02164 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/0228 , H01L21/02304 , H01L27/11519 , H01L27/11521 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： The present invention generally provides apparatus and method for processing a semiconductor substrate. Particularly, embodiments of the present invention relate to a method and apparatus for forming semiconductor devices having a conformal silicon oxide layer formed at low temperature. One embodiment of the present invention provides a method for forming a semiconductor gate structure. The method comprises forming a gate stack on a semiconductor substrate, forming a conformal silicon oxide layer on the semiconductor substrate using a low temperature cyclic method, and forming a spacer layer on the conformal silicon oxide layer.
摘要翻译： 本发明总体上提供了用于处理半导体衬底的装置和方法。 特别地，本发明的实施例涉及一种用于形成半导体器件的方法和装置，其具有在低温下形成的共形氧化硅层。 本发明的一个实施例提供一种形成半导体栅极结构的方法。 该方法包括在半导体衬底上形成栅叠层，在半导体衬底上使用低温循环法形成共形氧化硅层，并在保形氧化硅层上形成间隔层。
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公开(公告)号：US06656840B2
公开(公告)日：2003-12-02
申请号：US10136455
申请日：2002-04-29
申请人： Nagarajan Rajagopalan , Joe Feng , Christopher S Ngai , Meiyee (Maggie Le) Shek , Suketu A Parikh , Linh H Thanh
发明人： Nagarajan Rajagopalan , Joe Feng , Christopher S Ngai , Meiyee (Maggie Le) Shek , Suketu A Parikh , Linh H Thanh
IPC分类号： H01L2144
CPC分类号： H01L21/76834 , C23C18/1245 , C23C18/1254 , H01L21/31122 , H01L21/3185 , H01L21/76801 , H01L21/76807 , H01L21/76832 , H01L21/76838
摘要： A method for forming a microelectronics device is disclosed. In one embodiment, the method includes depositing a conductive structure on a substrate. A first layer comprising silicon and nitrogen is formed on the substrate. A second layer comprising silicon and nitrogen is then formed on the first layer. The nitrogen to silicon ratio in the first layer is greater than the nitrogen to silicon ratio in the second layer.
摘要翻译： 公开了一种用于形成微电子器件的方法。 在一个实施例中，该方法包括在衬底上沉积导电结构。 在衬底上形成包含硅和氮的第一层。 然后在第一层上形成包含硅和氮的第二层。 第一层中的氮与硅之比大于第二层中的氮与硅之比。
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5.发明申请ADHESION IMPROVEMENT OF DIELECTRIC BARRIER TO COPPER BY THE ADDITION OF THIN INTERFACE LAYER 审中-公开电介质阻挡层通过添加薄界面对铜的粘接改进公开(公告)号：US20120276301A1
公开(公告)日：2012-11-01
申请号：US13545738
申请日：2012-07-10
申请人： Yong-Won Lee , Sang M. Lee , Meiyee (Maggie Le) Shek , Weifeng Ye , Li-Qun Xia , Derek R. Witty , Thomas Nowak , Juan Carlos Rocha-Alvarez , Jigang Li
发明人： Yong-Won Lee , Sang M. Lee , Meiyee (Maggie Le) Shek , Weifeng Ye , Li-Qun Xia , Derek R. Witty , Thomas Nowak , Juan Carlos Rocha-Alvarez , Jigang Li
CPC分类号： H01L21/76832 , H01L21/7681 , H01L21/76826 , H01L21/76834 , H01L21/76849 , H01L21/76883 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments described herein provide a method of processing a substrate. The method includes depositing an interface adhesion layer between a conductive material and a dielectric material such that the interface adhesion layer provides increased adhesion between the conductive material and the dielectric material. In one embodiment a method for processing a substrate is provided. The method comprises depositing an interface adhesion layer on a substrate comprising a conductive material, exposing the interface adhesion layer to a nitrogen containing plasma, and depositing a dielectric layer on the interface adhesion layer after exposing the interface adhesion layer to the nitrogen containing plasma.
摘要翻译： 本文所述的实施例提供了一种处理衬底的方法。 该方法包括在导电材料和电介质材料之间沉积界面粘合层，使得界面粘合层在导电材料和电介质材料之间提供增加的粘合力。 在一个实施例中，提供了一种用于处理衬底的方法。 该方法包括在包括导电材料的基底上沉积界面粘附层，将界面粘附层暴露于含氮等离子体，以及在将界面粘附层暴露于含氮等离子体之后，在界面粘附层上沉积电介质层。
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6.发明申请METHODS AND APPARATUS OF CREATING AIRGAP IN DIELECTRIC LAYERS FOR THE REDUCTION OF RC DELAY 审中-公开用于减少RC延迟的电介质层中产生气泡的方法和装置公开(公告)号：US20110104891A1
公开(公告)日：2011-05-05
申请号：US12986809
申请日：2011-01-07
申请人： AMIR AL-BAYATI , Alexandros T. Demos , Kang Sub Yim , Mehul Naik , Zhenjiang David Cui , Mihaela Balseanu , Meiyee Maggie Le Shek , Li-Qun Xia
发明人： AMIR AL-BAYATI , Alexandros T. Demos , Kang Sub Yim , Mehul Naik , Zhenjiang David Cui , Mihaela Balseanu , Meiyee Maggie Le Shek , Li-Qun Xia
IPC分类号： H01L21/768
CPC分类号： H01L21/7682 , H01L21/3105 , H01L21/31111 , H01L21/31144 , H01L21/76825 , H01L21/76834 , H01L21/76849 , H01L21/76885
摘要： A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches.
摘要翻译： 一种用于在互连结构的电介质材料中产生气隙的方法和装置。 一个实施例提供了一种用于形成半导体结构的方法，包括在衬底上沉积第一介电层，在第一介电层中形成沟槽，用导电材料填充沟槽，平坦化导电材料以暴露第一介电层， 在导电材料和暴露的第一电介质层上的阻挡膜，在介电阻挡膜上沉积硬掩模层，在介电阻挡膜和硬掩模层中形成图案，以暴露衬底的选定区域，氧化至少一部分 在衬底的选定区域中的第一介电层，去除第一电介质层的氧化部分以在导电材料周围形成反向沟槽，以及在反向沟槽中形成气隙，同时在反向沟槽中沉积第二电介质材料。
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公开(公告)号：US20090093100A1
公开(公告)日：2009-04-09
申请号：US11869409
申请日：2007-10-09
申请人： Li-Qun Xia , Huiwen Xu , Mihaela Balseanu , Meiyee (Maggie Le) Shek , Derek R. Witty , Hichem M'Saad
发明人： Li-Qun Xia , Huiwen Xu , Mihaela Balseanu , Meiyee (Maggie Le) Shek , Derek R. Witty , Hichem M'Saad
IPC分类号： H01L21/76
CPC分类号： H01L21/76831 , C23C16/325 , H01L21/02112 , H01L21/02167 , H01L21/0217 , H01L21/02203 , H01L21/02274 , H01L21/02304 , H01L21/31144 , H01L21/3148 , H01L21/31633 , H01L21/76804 , H01L21/76807 , H01L21/7682 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76885 , H01L2221/1036
摘要： The present invention generally provides a method for forming multilevel interconnect structures, including multilevel interconnect structures that include an air gap. One embodiment provides a method for forming conductive lines in a semiconductor structure comprising forming trenches in a first dielectric layer, wherein air gaps are to be formed in the first dielectric layer, depositing a conformal dielectric barrier film in the trenches, wherein the conformal dielectric barrier film comprises a low k dielectric material configured to serve as a barrier against a wet etching chemistry used in forming the air gaps in the first dielectric layer, depositing a metallic diffusion barrier film over the conformal low k dielectric layer, and depositing a conductive material to fill the trenches.
摘要翻译： 本发明通常提供一种用于形成多层互连结构的方法，包括包括气隙的多层互连结构。 一个实施例提供了一种用于在半导体结构中形成导线的方法，包括在第一介电层中形成沟槽，其中在第一介电层中形成气隙，在沟槽中沉积共形介电阻挡膜，其中保形介电阻挡层 薄膜包括低k电介质材料，其被配置为用作抵抗用于形成第一介电层中的气隙的湿蚀刻化学物质的阻挡层，在保形低k电介质层上沉积金属扩散阻挡膜，并将导电材料沉积到 填补沟渠。
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公开(公告)号：US07851385B2
公开(公告)日：2010-12-14
申请号：US12241826
申请日：2008-09-30
IPC分类号： H01L21/31 , H01L21/469 , C23C16/40 , C23C16/00
CPC分类号： H01L21/31608 , C23C16/0272 , H01L21/02164 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/0228 , H01L21/02304 , H01L27/11519 , H01L27/11521 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： The present invention generally provides apparatus and method for processing a semiconductor substrate. Particularly, embodiments of the present invention relate to a method and apparatus for forming semiconductor devices having a conformal silicon oxide layer formed at low temperature. One embodiment of the present invention provides a method for forming a semiconductor gate structure. The method comprises forming a gate stack on a semiconductor substrate, forming a conformal silicon oxide layer on the semiconductor substrate using a low temperature cyclic method, and forming a spacer layer on the conformal silicon oxide layer.
摘要翻译： 本发明总体上提供了用于处理半导体衬底的装置和方法。 特别地，本发明的实施例涉及一种用于形成半导体器件的方法和装置，其具有在低温下形成的共形氧化硅层。 本发明的一个实施例提供一种形成半导体栅极结构的方法。 该方法包括在半导体衬底上形成栅堆叠，在半导体衬底上使用低温循环法形成共形氧化硅层，并在保形氧化硅层上形成间隔层。
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9.发明申请ADHESION IMPROVEMENT OF DIELECTRIC BARRIER TO COPPER BY THE ADDITION OF THIN INTERFACE LAYER 审中-公开电介质阻挡层通过添加薄界面对铜的粘接改进公开(公告)号：US20090107626A1
公开(公告)日：2009-04-30
申请号：US12258300
申请日：2008-10-24
申请人： Yong-Won Lee , Sang M. Lee , Meiyee(Maggie Le) Shek , Weifeng Ye , Li-Qun Xia , Derek R. Witty , Thomas Nowak , Juan Carlos Rocha-Alvarez , Jigang Li
发明人： Yong-Won Lee , Sang M. Lee , Meiyee(Maggie Le) Shek , Weifeng Ye , Li-Qun Xia , Derek R. Witty , Thomas Nowak , Juan Carlos Rocha-Alvarez , Jigang Li
IPC分类号： B32B37/00
CPC分类号： H01L21/76832 , H01L21/7681 , H01L21/76826 , H01L21/76834 , H01L21/76849 , H01L21/76883 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments described herein provide a method of processing a substrate. The method includes depositing an interface adhesion layer between a conductive material and a dielectric material such that the interface adhesion layer provides increased adhesion between the conductive material and the dielectric material. In one embodiment a method for processing a substrate is provided. The method comprises depositing an interface adhesion layer on a substrate comprising a conductive material, exposing the interface adhesion layer to a nitrogen containing plasma, and depositing a dielectric layer on the interface adhesion layer after exposing the interface adhesion layer to the nitrogen containing plasma.
摘要翻译： 本文所述的实施例提供了一种处理衬底的方法。 该方法包括在导电材料和电介质材料之间沉积界面粘合层，使得界面粘合层在导电材料和电介质材料之间提供增加的粘合力。 在一个实施例中，提供了一种用于处理衬底的方法。 该方法包括在包括导电材料的基底上沉积界面粘附层，将界面粘附层暴露于含氮等离子体，以及在将界面粘附层暴露于含氮等离子体之后，在界面粘附层上沉积电介质层。
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