公开(公告)号：US08222089B2

公开(公告)日：2012-07-17

申请号：US13033307

申请日：2011-02-23

Applicant: Kyoung-sei Choi ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

Inventor： Kyoung-sei Choi ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

IPC: H01J9/00

CPC classification number: H01L23/49838 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01079 ,  H05K1/0203 ,  H05K1/189 ,  H05K2201/09109 ,  H05K2201/1028 ,  H05K2201/10674 ,  H05K2203/1581 ,  H01L2924/00

Abstract: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Abstract translation: 公开了一种片上胶片（COF）型半导体封装以及使用其的器件。 COF型半导体封装可以包括包括顶表面和底表面的绝缘衬底，绝缘衬底的顶表面上的半导体器件，绝缘衬底的底表面上的散热部件，以及绝缘衬底的至少一个空间 绝缘基板的底表面和散热部件的顶表面。

公开(公告)号：US20090322362A1

公开(公告)日：2009-12-31

申请号：US12457775

申请日：2009-06-22

Applicant: So-Young Lim ,  Sang-Heui Lee

Inventor： So-Young Lim ,  Sang-Heui Lee

IPC: G01R31/02

CPC classification number: G01R31/2884 ,  G01R1/06 ,  G09G3/006 ,  H01L22/32 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/189 ,  H05K3/0052 ,  H05K2201/10681 ,  H01L2924/00

Abstract: A test pad structure may include a plurality of test pads and a plurality of connection leads. A plurality of the test pads may be sequentially arranged from a wiring pattern on a substrate and arranged in rows parallel with one another. The plurality of the test pads may include a first group of test pads having at least one pad arranged in a first row and a second group of test pads having at least two pads. A plurality of the connection leads may extend from end portions of the wiring pattern to be connected to the plurality of test pads. A plurality of the connection leads may include at least one inner lead passing between the at least two pads of the second group of the test pads arranged in a second row closest to the first group of the test pads. The at least one inner lead may be connected to at least one pad of the at least two pads of the second group of the test pads arranged in a third row next to the second row.

Abstract translation: 测试焊盘结构可以包括多个测试焊盘和多个连接引线。 多个测试焊盘可以从衬底上的布线图形顺序地布置并且彼此平行布置。 多个测试焊盘可以包括第一组测试焊盘，其具有布置在第一行中的至少一个焊盘和具有至少两个焊盘的第二组测试焊盘。 多个连接引线可以从要连接到多个测试焊盘的布线图案的端部延伸。 多个连接引线可以包括通过第二组测试焊盘的至少两个焊盘之间的至少一个内引线，该焊盘布置在最靠近第一组测试焊盘的第二行中。 所述至少一个内引线可以连接到布置在第二行旁边的第三行中的第二组测试焊盘的至少两个焊盘中的至少一个焊盘。

公开(公告)号：US20080111254A1

公开(公告)日：2008-05-15

申请号：US11940131

申请日：2007-11-14

Applicant: Ji-Yong PARK ,  Si-Hoon LEE ,  Sang-Heui LEE

Inventor： Ji-Yong PARK ,  Si-Hoon LEE ,  Sang-Heui LEE

IPC: H01L23/48 ,  H05K1/03 ,  H05K3/36

CPC classification number: H01L21/486 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H05K1/0287 ,  H05K1/0298 ,  H05K3/4084 ,  H05K2201/09681 ,  H05K2203/0108 ,  Y10T29/49126 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A pattern film in accordance with one aspect of the present invention includes a first film and a second film. A first pattern array is built in the first film. The second film is attached to the first film. Further, a second pattern array is built in the second film. The second pattern array is partially overlapped with the first pattern array. The first and the second pattern arrays may be electrically connected to each other by a pressurizing process. Thus, a time and a cost for manufacturing the pattern film may be reduced. As a result, a printed circuit board and a semiconductor package having the pattern film may also be manufactured at a low expense.

Abstract translation: 根据本发明的一个方面的图案膜包括第一膜和第二膜。 第一个图案阵列是建立在第一个电影。 第二部电影连接到第一部电影。 此外，在第二膜中构建第二图案阵列。 第二图案阵列与第一图案阵列部分重叠。 第一和第二图案阵列可以通过加压工艺彼此电连接。 因此，可以减少用于制造图案膜的时间和成本。 结果，也可以以低成本制造印刷电路板和具有图案膜的半导体封装。

公开(公告)号：US20090273076A1

公开(公告)日：2009-11-05

申请号：US12385731

申请日：2009-04-17

Applicant: Kyong-sei CHOI ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

Inventor： Kyong-sei CHOI ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

IPC: H01L23/498 ,  H01L23/36

CPC classification number: H01L23/49838 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01079 ,  H05K1/0203 ,  H05K1/189 ,  H05K2201/09109 ,  H05K2201/1028 ,  H05K2201/10674 ,  H05K2203/1581 ,  H01L2924/00

Abstract: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Abstract translation: 公开了一种片上胶片（COF）型半导体封装以及使用其的器件。 COF型半导体封装可以包括包括顶表面和底表面的绝缘衬底，绝缘衬底的顶表面上的半导体器件，绝缘衬底的底表面上的散热部件，以及绝缘衬底的至少一个空间 绝缘基板的底表面和散热部件的顶表面。

公开(公告)号：US20110143625A1

公开(公告)日：2011-06-16

申请号：US13033307

申请日：2011-02-23

Applicant: Kyoung-sei Choi ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

Inventor： Kyoung-sei Choi ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

IPC: H01J9/00

CPC classification number: H01L23/49838 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01079 ,  H05K1/0203 ,  H05K1/189 ,  H05K2201/09109 ,  H05K2201/1028 ,  H05K2201/10674 ,  H05K2203/1581 ,  H01L2924/00

Abstract: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Abstract translation: 公开了一种片上胶片（COF）型半导体封装以及使用其的器件。 COF型半导体封装可以包括包括顶表面和底表面的绝缘衬底，绝缘衬底的顶表面上的半导体器件，绝缘衬底的底表面上的散热部件，以及绝缘衬底的至少一个空间 绝缘基板的底表面和散热部件的顶表面。

公开(公告)号：US07915727B2

公开(公告)日：2011-03-29

申请号：US12385731

申请日：2009-04-17

Applicant: Kyoung-sei Choi ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

Inventor： Kyoung-sei Choi ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

IPC: H01L23/498 ,  H01L23/36

CPC classification number: H01L23/49838 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01079 ,  H05K1/0203 ,  H05K1/189 ,  H05K2201/09109 ,  H05K2201/1028 ,  H05K2201/10674 ,  H05K2203/1581 ,  H01L2924/00

Abstract: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Abstract translation: 公开了一种片上胶片（COF）型半导体封装以及使用其的器件。 COF型半导体封装可以包括包括顶表面和底表面的绝缘衬底，绝缘衬底的顶表面上的半导体器件，绝缘衬底的底表面上的散热部件，以及绝缘衬底的至少一个空间 绝缘基板的底表面和散热部件的顶表面。

公开(公告)号：US20080119061A1

公开(公告)日：2008-05-22

申请号：US11758175

申请日：2007-06-05

Applicant: Ji-hwan HWANG ,  Dong-han KIM ,  Chul-woo KIM ,  Sang-heui LEE ,  Kwang-jin BAE

Inventor： Ji-hwan HWANG ,  Dong-han KIM ,  Chul-woo KIM ,  Sang-heui LEE ,  Kwang-jin BAE

IPC: H01L23/48 ,  H05K1/00

CPC classification number: H01L23/49572 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K1/189 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/094 ,  H05K2201/09709 ,  H05K2201/10674 ,  H05K2201/10681 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor chip is disclosed and includes a plurality of bond pads disposed on a semiconductor chip, and a plurality of chip bumps of different heights disposed on a corresponding bond pad.

Abstract translation: 公开了一种半导体芯片，并且包括设置在半导体芯片上的多个接合焊盘以及设置在相应的焊盘上的不同高度的多个芯片凸块。