公开(公告)号：US20140374902A1

公开(公告)日：2014-12-25

申请号：US14267259

申请日：2014-05-01

申请人： Jang-Woo LEE ,  Jong-Bo SHIM ,  Kyoung-sei CHOI

发明人： Jang-Woo LEE ,  Jong-Bo SHIM ,  Kyoung-sei CHOI

IPC分类号： H01L23/00 ,  H01L23/36

CPC分类号： H01L23/36 ,  H01L23/367 ,  H01L23/3736 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03312 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05573 ,  H01L2224/05578 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45169 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/94 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stack type semiconductor package includes: a lower semiconductor package including a lower package substrate, and a lower semiconductor chip which is mounted on the lower package substrate and includes a first surface facing a top surface of the lower package substrate and a second surface opposite to the first surface; an upper semiconductor package including an upper package substrate and an upper semiconductor chip which is mounted on the upper package substrate; an inter-package connection unit which connects the lower package substrate and the upper package substrate; a heat dissipation member which is formed on the second surface of the lower semiconductor chip; and an interconnection unit which is formed on a bottom surface of the upper package substrate, and is adhered to the heat dissipation member to connect the lower semiconductor chip and the upper package substrate.

摘要翻译： 堆叠型半导体封装包括：下半导体封装，包括下封装衬底，以及下半导体芯片，其安装在下封装衬底上，并且包括面向下封装衬底的顶表面的第一表面和与下封装衬底相对的第二表面 第一面; 上半导体封装，包括上封装基板和安装在上封装基板上的上半导体芯片; 连接下封装基板和上封装基板的封装间连接单元; 形成在下半导体芯片的第二表面上的散热构件; 以及互连单元，其形成在所述上封装基板的底表面上，并且粘附到所述散热构件以连接所述下半导体芯片和所述上封装基板。

公开(公告)号：US08796158B2

公开(公告)日：2014-08-05

申请号：US13346041

申请日：2012-01-09

申请人： Kyoung-sei Choi

发明人： Kyoung-sei Choi

IPC分类号： H01L21/469 ,  H01L23/053 ,  H01L21/48 ,  H01L21/312 ,  H01L23/31

CPC分类号： H01L21/4846 ,  H01L21/3122 ,  H01L23/3107 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H05K1/0393 ,  H05K3/045 ,  H05K3/06 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/243 ,  H05K3/28 ,  H05K3/388 ,  H05K2201/0108 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2203/0108 ,  Y10T29/49227 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method for forming a circuit pattern forming region in an insulating substrate may include preparing a metallic pattern, coating a polymer solution on a casting vessel, precuring the polymer solution, and forming an imprinted circuit pattern forming region in the precured polymer solution using the metallic pattern.

摘要翻译： 用于在绝缘基板中形成电路图案形成区域的方法可以包括制备金属图案，在浇铸容器上涂覆聚合物溶液，预聚合物溶液，以及在预固化聚合物溶液中形成印记电路图案形成区域，使用金属 模式。

公开(公告)号：US08575746B2

公开(公告)日：2013-11-05

申请号：US11878016

申请日：2007-07-20

申请人： Si-Hoon Lee ,  Sa-Yoon Kang ,  Kyoung-Sei Choi

发明人： Si-Hoon Lee ,  Sa-Yoon Kang ,  Kyoung-Sei Choi

IPC分类号： H01L23/14 ,  H01L23/34

CPC分类号： H01L23/4985 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/73204

摘要： A Chip on Flexible Printed Circuit (COF) type semiconductor package may include a flexible film, a semiconductor IC chip on the flexible film, and a heating pad on the flexible film.

摘要翻译： 柔性印刷电路（COF）型半导体封装上的芯片可以包括柔性膜，柔性膜上的半导体IC芯片和柔性膜上的加热垫。

公开(公告)号：US20100044851A1

公开(公告)日：2010-02-25

申请号：US12461639

申请日：2009-08-19

申请人： Yun-Seok Choi ,  Hee-Seok Lee ,  Kyoung-Sei Choi

发明人： Yun-Seok Choi ,  Hee-Seok Lee ,  Kyoung-Sei Choi

IPC分类号： H01L23/31 ,  H01L21/60 ,  H01L23/488

CPC分类号： H01L21/563 ,  H01L23/295 ,  H01L23/60 ,  H01L24/16 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Flip chip packages and methods of manufacturing the same are provided, the flip chip packages may include a package substrate, a semiconductor chip, conductive bumps, a ground pattern and an underfilling layer. The semiconductor chip may be over the package substrate. The conductive bumps may be between the semiconductor chip and the package substrate to electrically connect the semiconductor chip and the package substrate with each other. The ground pattern may ground one of the package substrate and the semiconductor chip. The underfilling layer may be between the package substrate and the semiconductor chip to surround the conductive bumps. The underfilling layer may have a diode selectively located between the ground pattern and the conductive bumps by electrostatic electricity applied to the underfilling layer to protect the semiconductor chip from the electrostatic electricity.

摘要翻译： 提供了倒装芯片封装及其制造方法，倒装芯片封装可以包括封装衬底，半导体芯片，导电凸块，接地图案和底部填充层。 半导体芯片可以在封装衬底之上。 导电凸块可以在半导体芯片和封装基板之间，以将半导体芯片和封装基板彼此电连接。 接地图可以将封装衬底和半导体芯片之一接地。 底部填充层可以在封装衬底和半导体芯片之间以包围导电凸块。 底部填充层可以通过施加到底部填充层的静电来选择性地位于接地图案和导电凸块之间的二极管，以保护半导体芯片免受静电。

公开(公告)号：US20070007664A1

公开(公告)日：2007-01-11

申请号：US11428169

申请日：2006-06-30

申请人： Chung-Sun LEE ,  Yong-Hwan KWON ,  Kyoung-Sei CHOI ,  Woon-Byung KANG

发明人： Chung-Sun LEE ,  Yong-Hwan KWON ,  Kyoung-Sei CHOI ,  Woon-Byung KANG

IPC分类号： H01L23/48 ,  H01L21/00 ,  H01L21/44

CPC分类号： H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/562 ,  H01L24/11 ,  H01L24/12 ,  H01L24/27 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

摘要： Provided are a semiconductor package having a semiconductor chip, a rear surface of which is molded, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip including a wafer and a metal pad formed on a front surface of the wafer; a solder ball formed on a front surface of the wafer, and electrically connected to the metal pad; and a reinforcing member formed on a rear surface of the wafer. The reinforcing member is formed of an epoxy molding compound, and the reinforcing member protrudes at least 5 μm from side surfaces of the semiconductor chip.

摘要翻译： 提供一种半导体封装，其具有半导体芯片，其后表面被模制，以及制造半导体封装的方法。 半导体封装包括：半导体芯片，包括晶片和形成在晶片前表面上的金属焊盘; 形成在所述晶片的前表面上并且电连接到所述金属焊盘的焊球; 以及形成在晶片的后表面上的加强构件。 加强构件由环氧树脂模塑料形成，并且加强构件从半导体芯片的侧表面突出至少5微米。

公开(公告)号：US20060071303A1

公开(公告)日：2006-04-06

申请号：US11218260

申请日：2005-08-31

申请人： Chung-Sun Lee ,  Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Kyoung-Sei Choi

发明人： Chung-Sun Lee ,  Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Kyoung-Sei Choi

IPC分类号： H01L23/58

CPC分类号： H01L23/13 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/838 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/3025 ,  H05K1/0271 ,  H05K1/189 ,  H05K3/0038 ,  H05K3/027 ,  H05K3/22 ,  H05K2201/09072 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05099

摘要： Embodiments of the present invention are directed to a film substrate of a semiconductor package. The film substrate of the semiconductor package comprises a thin film insulating substrate and a thin copper circuit pattern. An inter-pattern groove between the thin copper circuit patterns is formed by laser etching. Accordingly, the embodiment improves electrical contact between the film substrate and a semiconductor chip mounted thereon, and improves the manufacturing process for the film substrate by adopting a simple laser machining to form the thin copper circuit pattern in lieu of a traditional wet-etching process that undergoes complex lithography steps.

摘要翻译： 本发明的实施例涉及一种半导体封装的薄膜基片。 半导体封装的薄膜基板包括薄膜绝缘基板和薄铜电路图案。 通过激光蚀刻形成薄铜电路图案之间的图案间凹槽。 因此，本实施方式改善了薄膜基板与安装在其上的半导体芯片之间的电接触，并且通过采用简单的激光加工来形成薄铜电路图案来代替薄的基板的制造工艺来代替传统的湿式蚀刻工艺， 经历复杂的光刻步骤。

公开(公告)号：US20060003568A1

公开(公告)日：2006-01-05

申请号：US11086614

申请日：2005-03-21

申请人： Kyoung-Sei Choi ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Chung-Sun Lee

发明人： Kyoung-Sei Choi ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Chung-Sun Lee

IPC分类号： H01L21/44

CPC分类号： H05K3/28 ,  H05K1/036 ,  H05K1/0393 ,  H05K3/101 ,  H05K3/107 ,  H05K3/1258 ,  H05K2201/0129 ,  H05K2201/0162 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/0759 ,  H05K2203/1105 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/4916

摘要： A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern, thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the manufacturing time and cost may be reduced. A profile of the wiring pattern may be determined by the shape of an impression pattern of a mold. This may establish the top width of inner and outer leads and incorporate fine pad pitch. Although ILB and OLB process may use an NCP, connection reliability may be established due to the soft and elastic wiring pattern.

摘要翻译： 根据本发明的制造带布线板的方法可以在形成布线图案中采用压印工艺，从而减少了用于制造带布线板的工艺的数量，并允许制造工艺在单个生产线中进行。 因此，制造时间和成本可能降低。 布线图案的轮廓可以通过模具的印模图案的形状来确定。 这可以建立内部和外部引线的顶部宽度并且结合细小的垫间距。 虽然ILB和OLB过程可能使用NCP，但是由于软和弹性布线图案可能建立连接可靠性。

公开(公告)号：US20110304763A1

公开(公告)日：2011-12-15

申请号：US13095155

申请日：2011-04-27

申请人： Mi-Na Choi ,  Kyoung-Sei Choi ,  Hee-Seok Lee ,  Yong-Hoon Kim ,  Hee-Jung Hwang ,  Se-Ran Bae

发明人： Mi-Na Choi ,  Kyoung-Sei Choi ,  Hee-Seok Lee ,  Yong-Hoon Kim ,  Hee-Jung Hwang ,  Se-Ran Bae

IPC分类号： H04N5/225 ,  H01L31/0216

CPC分类号： H04N5/2253

摘要： An image sensor chip, a camera module, and devices incorporating the image sensor chip and camera module include a light receiving unit on which light is incident, a logic unit provided to surround the light receiving unit, and an electromagnetic wave shielding layer formed on the logic unit and not formed on the light receiving unit.

摘要翻译： 图像传感器芯片，相机模块以及包含图像传感器芯片和相机模块的装置包括光入射的光接收单元，围绕光接收单元的逻辑单元和形成在该光接收单元上的电磁波屏蔽层 逻辑单元，并且不形成在光接收单元上。

公开(公告)号：US07888237B2

公开(公告)日：2011-02-15

申请号：US12265165

申请日：2008-11-05

申请人： Dong-Han Kim ,  Kyoung-Sei Choi ,  Chul-woo Kim

发明人： Dong-Han Kim ,  Kyoung-Sei Choi ,  Chul-woo Kim

IPC分类号： H01L21/00

CPC分类号： H01L21/67092 ,  B28D5/0011 ,  H01L21/78

摘要： A method of cutting a semiconductor wafer includes preparing a semiconductor wafer including a scribe region and a chip region, forming a groove in the scribe region, loading the semiconductor wafer with the groove formed therein in a chamber, and cutting the semiconductor wafer into a plurality of chips through increasing a pressure of the chamber by a first pressure change rate, and then reducing the pressure of the chamber by a second pressure change rate.

摘要翻译： 切割半导体晶片的方法包括制备包括划线区域和芯片区域的半导体晶片，在刻划区域形成沟槽，将其中形成有槽的半导体晶片装载在室中，并将半导体晶片切割成多个 通过增加室的压力达到第一压力变化率，然后将室的压力降低第二压力变化率。

公开(公告)号：US20100005652A1

公开(公告)日：2010-01-14

申请号：US12458430

申请日：2009-07-13

申请人： Dong-Han Kim ,  Kyoung-Sei Choi ,  Kyong-Soon Cho

发明人： Dong-Han Kim ,  Kyoung-Sei Choi ,  Kyong-Soon Cho

IPC分类号： H05K3/20 ,  H01S4/00

CPC分类号： H05K3/207 ,  H05K1/0393 ,  H05K3/1216 ,  H05K3/386 ,  H05K2203/0113 ,  Y10T29/49002 ,  Y10T29/49128 ,  Y10T29/4913

摘要： Disclosed is a method of manufacturing a wiring substrate, a tape package using the wiring substrate, and a display device using the wiring substrate. In a method of manufacturing a wiring substrate, a screen may be disposed on a base plate, the screen having openings for forming wirings. A conductive paste may be coated in the openings of the screen. A substrate may be on the screen, the conductive paste being coated in the openings of the screen. The conductive paste may be hardened to be adhered to the substrate. The base plate and the screen may be removed from the substrate to form wirings on the substrate. Because the wirings may be formed using a glass substrate having heat-resisting properties by simplified processes, thermal deflections of the substrate and dimension variations in manufacturing processes may be reduced or minimized.

摘要翻译： 公开了一种制造布线基板的方法，使用该布线基板的带封装以及使用该布线基板的显示装置。 在制造布线基板的方法中，可以在基板上设置屏幕，该屏幕具有用于形成布线的开口。 可以在屏幕的开口中涂覆导电糊。 衬底可以在屏幕上，导电膏被涂覆在屏幕的开口中。 导电膏可以硬化以粘附到基底上。 基板和屏幕可以从基板移除以在基板上形成布线。 由于可以通过简化的工艺使用具有耐热性的玻璃基板形成布线，所以可以减小或最小化基板的热偏转和制造工艺中的尺寸变化。