公开(公告)号：US20120021600A1

公开(公告)日：2012-01-26

申请号：US13184810

申请日：2011-07-18

Applicant: Sang-Uk Han ,  Dae-Woo Son ,  Kwan-Jai Lee ,  Ye-Chung Chung ,  Jeong-Kyu Ha ,  Yun-Young Kim

Inventor： Sang-Uk Han ,  Dae-Woo Son ,  Kwan-Jai Lee ,  Ye-Chung Chung ,  Jeong-Kyu Ha ,  Yun-Young Kim

IPC: H01L21/283

CPC classification number: H01L23/4985 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a film circuit substrate and a method of fabricating a chip package. The method of fabricating a film circuit substrate can include providing a base film including a chip packaging area to package a chip and a separation area to separate the two chip packaging areas from each other, the separation area including a cut area and an uncut area; forming a reserve interconnection pattern having a first height on the base film; and forming an interconnection pattern having a second height that is lower than the first height on the out area by selectively etching the reserve interconnection pattern of the cut area.

Abstract translation: 薄膜电路基板的制造方法以及芯片封装的制造方法。 制造薄膜电路基板的方法可以包括提供包括芯片封装区域以包装芯片的基膜和分离区域，以将两个芯片封装区域彼此分离，分离区域包括切割区域和未切割区域; 在基膜上形成具有第一高度的保留互连图案; 以及通过选择性地蚀刻所述切割区域的预留互连图案，形成具有低于所述外部区域上的所述第一高度的第二高度的互连图案。

公开(公告)号：US07902647B2

公开(公告)日：2011-03-08

申请号：US12627361

申请日：2009-11-30

Applicant: Ye-chung Chung ,  Sa-yoon Kang

Inventor： Ye-chung Chung ,  Sa-yoon Kang

IPC: H01L23/495

CPC classification number: H01L23/4985 ,  G02F1/13452 ,  H01L23/3157 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15151 ,  H01L2924/181 ,  H05K3/281 ,  H05K3/361 ,  H05K2201/09154 ,  H05K2201/09727 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: A device is provided in which a glass panel having beveled edge is flexibly connected to a TAB package. The outer lead portions of the TAB package include an end portion of first width connected to a connection pattern on the glass panel, a terminal portion having a second width greater than the first width, and a transition portion having a width that varies between the first and second widths. When the TAB package is connected the transition portion of the respective outer lead portions are disposed over the beveled edge of the glass panel.

Abstract translation: 提供了一种装置，其中具有斜边的玻璃面板与TAB封装灵活地连接。 TAB封装的外引线部分包括连接到玻璃面板上的连接图案的第一宽度的端部，具有大于第一宽度的第二宽度的端子部分和具有在第一宽度之间变化的宽度的过渡部分 和第二宽度。 当连接TAB封装时，相应的外引线部分的过渡部分设置在玻璃面板的斜边上。

公开(公告)号：US20100001392A1

公开(公告)日：2010-01-07

申请号：US12458231

申请日：2009-07-06

Applicant: Young-sang Cho ,  Dong-han Kim ,  Dae-woo Son ,  Ye-chung Chung

Inventor： Young-sang Cho ,  Dong-han Kim ,  Dae-woo Son ,  Ye-chung Chung

IPC: H01L23/544 ,  H01L23/488

CPC classification number: H01L23/544 ,  H01L23/498 ,  H01L24/81 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/81121 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082

Abstract: Provided is a semiconductor package including a substrate and a semiconductor chip formed on the substrate. The semiconductor chip may include a chip alignment mark on a surface of the semiconductor chip, and wiring patterns formed on a surface of the substrate, wherein the chip alignment mark is bonded to the wiring patterns. Accordingly, the surface area of the semiconductor chip may be reduced.

Abstract translation: 提供了一种半导体封装，其包括形成在基板上的基板和半导体芯片。 半导体芯片可以包括在半导体芯片的表面上的芯片对准标记，以及形成在基板的表面上的布线图案，其中芯片对准标记被接合到布线图案。 因此，可以减小半导体芯片的表面积。

公开(公告)号：US07329597B2

公开(公告)日：2008-02-12

申请号：US11261260

申请日：2005-10-28

Applicant: Ye-Chung Chung ,  Dong-Han Kim ,  Sa-Yoon Kang

Inventor： Ye-Chung Chung ,  Dong-Han Kim ,  Sa-Yoon Kang

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L23/49838 ,  H01L21/4839 ,  H01L23/49572 ,  H01L23/4985 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor chip, having an active surface including a peripheral area and a central area, presents a connection area formed on a portion of the peripheral area. The semiconductor chip includes output pads formed in the peripheral area of the active surface and input pads formed in the central area of the active surface. The input pads may be connected to wiring patterns of a TAB tape passing over the connection area.

Abstract translation: 具有包括周边区域和中心区域的活性表面的半导体芯片具有形成在周边区域的一部分上的连接区域。 半导体芯片包括形成在有源表面的周边区域中的输出焊盘和形成在有源表面的中心区域中的输入焊盘。 输入焊盘可以连接到通过连接区域的TAB磁带的布线图案。

公开(公告)号：US07109575B2

公开(公告)日：2006-09-19

申请号：US10862337

申请日：2004-06-08

Applicant: Sa-Yoon Kang ,  Dong-Han Kim ,  Ye-Chung Chung

Inventor： Sa-Yoon Kang ,  Dong-Han Kim ,  Ye-Chung Chung

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/12 ,  H01L23/52 ,  H01L29/40

CPC classification number: G02F1/13452 ,  H01L23/5387 ,  H01L2224/16 ,  H01L2924/07811 ,  H05K1/118 ,  H05K1/147 ,  H05K2201/068 ,  H05K2201/10681 ,  H01L2924/00

Abstract: Provided are a flexible film package module and a method of manufacturing the same that can be adapted for manufacture at lower cost and/or to adapt the characteristics of the flexible film package module for specific applications. The lower-cost flexible film package module includes a tape film that combines both a first insulating substrate, typically formed from a higher-cost polyimide material, and a second insulating substrate, typically formed from an insulating material or materials that are less expensive and/or provide modified performance when compared with the first insulating material. Both the first and second substrates will include complementary circuit patterns that will be electrically and physically connected to allow the composite substrate to function as a unitary substrate. The first and second substrates will also include connection regions that may be adapted for connection to printed circuit boards and/or electronic devices such as liquid crystal displays.

Abstract translation: 提供了一种柔性膜封装模块及其制造方法，其可以适于以更低成本制造和/或适应特定应用的柔性膜封装模块的特性。 较低成本的柔性膜封装模块包括一个胶带，其将通常由较高成本的聚酰亚胺材料形成的第一绝缘基板和通常由绝缘材料形成的第二绝缘基板或较便宜的材料和/ 或者与第一绝缘材料相比提供改进的性能。 第一和第二基板都将包括互补的电路图案，其将被电和物理连接，以允许复合基板作为整体基板。 第一和第二基板还将包括可适于连接到印刷电路板和/或诸如液晶显示器的电子设备的连接区域。

公开(公告)号：US09557616B2

公开(公告)日：2017-01-31

申请号：US13242394

申请日：2011-09-23

Applicant: Ye-Chung Chung ,  Hee-seok Lee ,  Yun-Seok Choi ,  Keung-Beum Kim

Inventor： Ye-Chung Chung ,  Hee-seok Lee ,  Yun-Seok Choi ,  Keung-Beum Kim

IPC: G06F3/038 ,  H03K3/00 ,  G02F1/1345

CPC classification number: H01L27/1244 ,  G02F1/13452 ,  G09G3/20 ,  G09G2300/0426 ,  G09G2310/08 ,  G09G2330/021 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13124 ,  H01L2224/13639 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/1426 ,  H05K1/148

Abstract: An image display panel assembly includes a flexible printed circuit (FPC), an image display panel, a gate driver integrated circuit (IC) package, and a source driver IC package. The FPC is configured to receive gate and source driving signals. The image display panel is electrically connected to the FPC, and includes a gate driving signal transfer pattern along a first edge of the image display panel, a source driving signal transfer pattern along a second edge adjacent to the first end, and a plurality of pixels. The gate driver integrated circuit (IC) package is configured to receive the gate driving signal through the gate driving signal transfer pattern and provide the gate driving signal to the plurality of pixels. The source driver IC package is configured to receive the source driving signal through the source driving signal transfer pattern and provide the source driving signal to the plurality of pixels.

Abstract translation: 图像显示面板组件包括柔性印刷电路（FPC），图像显示面板，栅极驱动器集成电路（IC）封装以及源极驱动器IC封装。 FPC被配置为接收门和源驱动信号。 图像显示面板电连接到FPC，并且包括沿着图像显示面板的第一边缘的栅极驱动信号传递图案，沿着与第一端相邻的第二边缘的源极驱动信号传递图案，以及多个像素 。 栅极驱动器集成电路（IC）封装被配置为通过栅极驱动信号传输图案接收栅极驱动信号，并将栅极驱动信号提供给多个像素。 源极驱动器IC封装被配置为通过源极驱动信号传输图案接收源极驱动信号，并将源极驱动信号提供给多个像素。

公开(公告)号：US20120075268A1

公开(公告)日：2012-03-29

申请号：US13242394

申请日：2011-09-23

Applicant: Ye-Chung Chung ,  Hee-seok Lee ,  Yun-Seok Choi ,  Keung-Beum Kim

Inventor： Ye-Chung Chung ,  Hee-seok Lee ,  Yun-Seok Choi ,  Keung-Beum Kim

IPC: G09G5/00 ,  H03L5/00

CPC classification number: H01L27/1244 ,  G02F1/13452 ,  G09G3/20 ,  G09G2300/0426 ,  G09G2310/08 ,  G09G2330/021 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13124 ,  H01L2224/13639 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/1426 ,  H05K1/148

Abstract: An image display panel assembly includes a flexible printed circuit (FPC), an image display panel, a gate driver integrated circuit (IC) package, and a source driver IC package. The FPC is configured to receive gate and source driving signals. The image display panel is electrically connected to the FPC, and includes a gate driving signal transfer pattern along a first edge of the image display panel, a source driving signal transfer pattern along a second edge adjacent to the first end, and a plurality of pixels. The gate driver integrated circuit (IC) package is configured to receive the gate driving signal through the gate driving signal transfer pattern and provide the gate driving signal to the plurality of pixels. The source driver IC package is configured to receive the source driving signal through the source driving signal transfer pattern and provide the source driving signal to the plurality of pixels.

Abstract translation: 图像显示面板组件包括柔性印刷电路（FPC），图像显示面板，栅极驱动器集成电路（IC）封装以及源极驱动器IC封装。 FPC被配置为接收门和源驱动信号。 图像显示面板电连接到FPC，并且包括沿着图像显示面板的第一边缘的栅极驱动信号传递图案，沿着与第一端相邻的第二边缘的源极驱动信号传递图案，以及多个像素 。 栅极驱动器集成电路（IC）封装被配置为通过栅极驱动信号传输图案接收栅极驱动信号，并将栅极驱动信号提供给多个像素。 源极驱动器IC封装被配置为通过源极驱动信号传输图案接收源极驱动信号，并将源极驱动信号提供给多个像素。

公开(公告)号：US07649246B2

公开(公告)日：2010-01-19

申请号：US11396526

申请日：2006-04-04

Applicant: Ye-chung Chung ,  Sa-yoon Kang

Inventor： Ye-chung Chung ,  Sa-yoon Kang

IPC: H01L23/495

CPC classification number: H01L23/4985 ,  G02F1/13452 ,  H01L23/3157 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15151 ,  H01L2924/181 ,  H05K3/281 ,  H05K3/361 ,  H05K2201/09154 ,  H05K2201/09727 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: A device is provided in which a glass panel having beveled edge is flexibly connected to a TAB package. The outer lead portions of the TAB package include an end portion of first width connected to a connection pattern on the glass panel, a terminal portion having a second width greater than the first width, and a transition portion having a width that varies between the first and second widths. When the TAB package is connected the transition portion of the respective outer lead portions are disposed over the beveled edge of the glass panel.

Abstract translation: 提供了一种装置，其中具有斜边的玻璃面板与TAB封装灵活地连接。 TAB封装的外引线部分包括连接到玻璃面板上的连接图案的第一宽度的端部，具有大于第一宽度的第二宽度的端子部分和具有在第一宽度之间变化的宽度的过渡部分 和第二宽度。 当连接TAB封装时，相应的外引线部分的过渡部分设置在玻璃面板的斜边上。

公开(公告)号：US20090273076A1

公开(公告)日：2009-11-05

申请号：US12385731

申请日：2009-04-17

Applicant: Kyong-sei CHOI ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

Inventor： Kyong-sei CHOI ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

IPC: H01L23/498 ,  H01L23/36

CPC classification number: H01L23/49838 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01079 ,  H05K1/0203 ,  H05K1/189 ,  H05K2201/09109 ,  H05K2201/1028 ,  H05K2201/10674 ,  H05K2203/1581 ,  H01L2924/00

Abstract: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Abstract translation: 公开了一种片上胶片（COF）型半导体封装以及使用其的器件。 COF型半导体封装可以包括包括顶表面和底表面的绝缘衬底，绝缘衬底的顶表面上的半导体器件，绝缘衬底的底表面上的散热部件，以及绝缘衬底的至少一个空间 绝缘基板的底表面和散热部件的顶表面。

公开(公告)号：US20090065934A1

公开(公告)日：2009-03-12

申请号：US12232099

申请日：2008-09-10

Applicant: Ye-Chung Chung ,  Don-Han Kim

Inventor： Ye-Chung Chung ,  Don-Han Kim

IPC: H01L23/485 ,  H01L21/60 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K1/111 ,  H01L23/4985 ,  H01L24/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15173 ,  H05K1/189 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09709 ,  H05K2201/10674 ,  H05K2201/10681 ,  Y02P70/611 ,  Y10T29/49155

Abstract: A wiring substrate may include a base film, a plurality of wires, a first insulation member and a second insulation member. The base film may have a chip-mounting region where a semiconductor chip may be mounted thereon. The wires may extend from the chip-mounting region and the wires may include adhesive end portions that may be electrically connected to the semiconductor chip. The first insulation member may cover portions of the wires outside the chip-mounting region thereof. The second insulation member may cover portions of the wire inside the chip-mounting region, the adhesive end portion of the wire being exposed by the second insulation member.

Abstract translation: 布线基板可以包括基膜，多根导线，第一绝缘构件和第二绝缘构件。 基膜可以具有可以在其上安装半导体芯片的芯片安装区域。 电线可以从芯片安装区域延伸，并且电线可以包括可以电连接到半导体芯片的粘合剂端部。 第一绝缘构件可以覆盖其芯片安装区域外部的电线的部分。 第二绝缘构件可以覆盖芯片安装区域内的线的部分，线的粘合端部被第二绝缘构件暴露。