公开(公告)号：US07902647B2

公开(公告)日：2011-03-08

申请号：US12627361

申请日：2009-11-30

Applicant: Ye-chung Chung ,  Sa-yoon Kang

Inventor： Ye-chung Chung ,  Sa-yoon Kang

IPC: H01L23/495

CPC classification number: H01L23/4985 ,  G02F1/13452 ,  H01L23/3157 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15151 ,  H01L2924/181 ,  H05K3/281 ,  H05K3/361 ,  H05K2201/09154 ,  H05K2201/09727 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: A device is provided in which a glass panel having beveled edge is flexibly connected to a TAB package. The outer lead portions of the TAB package include an end portion of first width connected to a connection pattern on the glass panel, a terminal portion having a second width greater than the first width, and a transition portion having a width that varies between the first and second widths. When the TAB package is connected the transition portion of the respective outer lead portions are disposed over the beveled edge of the glass panel.

Abstract translation: 提供了一种装置，其中具有斜边的玻璃面板与TAB封装灵活地连接。 TAB封装的外引线部分包括连接到玻璃面板上的连接图案的第一宽度的端部，具有大于第一宽度的第二宽度的端子部分和具有在第一宽度之间变化的宽度的过渡部分 和第二宽度。 当连接TAB封装时，相应的外引线部分的过渡部分设置在玻璃面板的斜边上。

公开(公告)号：US07329597B2

公开(公告)日：2008-02-12

申请号：US11261260

申请日：2005-10-28

Applicant: Ye-Chung Chung ,  Dong-Han Kim ,  Sa-Yoon Kang

Inventor： Ye-Chung Chung ,  Dong-Han Kim ,  Sa-Yoon Kang

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L23/49838 ,  H01L21/4839 ,  H01L23/49572 ,  H01L23/4985 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor chip, having an active surface including a peripheral area and a central area, presents a connection area formed on a portion of the peripheral area. The semiconductor chip includes output pads formed in the peripheral area of the active surface and input pads formed in the central area of the active surface. The input pads may be connected to wiring patterns of a TAB tape passing over the connection area.

Abstract translation: 具有包括周边区域和中心区域的活性表面的半导体芯片具有形成在周边区域的一部分上的连接区域。 半导体芯片包括形成在有源表面的周边区域中的输出焊盘和形成在有源表面的中心区域中的输入焊盘。 输入焊盘可以连接到通过连接区域的TAB磁带的布线图案。

公开(公告)号：US20080029923A1

公开(公告)日：2008-02-07

申请号：US11872580

申请日：2007-10-15

Applicant: Kyoung-Sei CHOI ,  Sa-Yoon KANG ,  Yong-Hwan KWON ,  Chung-Sun LEE

Inventor： Kyoung-Sei CHOI ,  Sa-Yoon KANG ,  Yong-Hwan KWON ,  Chung-Sun LEE

IPC: C04B35/00

CPC classification number: H05K3/28 ,  H05K1/036 ,  H05K1/0393 ,  H05K3/101 ,  H05K3/107 ,  H05K3/1258 ,  H05K2201/0129 ,  H05K2201/0162 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/0759 ,  H05K2203/1105 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/4916

Abstract: A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the manufacturing time and cost may be reduced. A profile of the wiring pattern may be determined by the shape of an impression pattern of a mold. This may establish the top width of inner and outer leads and incorporate fine pad pitch. Although ILB and OLB process may use an NCP, connection reliability may be established due to the soft and elastic wiring pattern.

Abstract translation: 根据本发明的制造带布线板的方法可以在形成布线图案中采用压印工艺，从而减少制造带布线板的工艺的数量，并允许制造工艺在单个生产线中进行。 因此，制造时间和成本可能降低。 布线图案的轮廓可以通过模具的印模图案的形状来确定。 这可以建立内部和外部引线的顶部宽度并且结合细小的垫间距。 虽然ILB和OLB过程可能使用NCP，但是由于软和弹性布线图案可能建立连接可靠性。

公开(公告)号：US07183660B2

公开(公告)日：2007-02-27

申请号：US10949091

申请日：2004-09-23

Applicant: Si-Hoon Lee ,  Sa-Yoon Kang ,  Dong-Han Kim

Inventor： Si-Hoon Lee ,  Sa-Yoon Kang ,  Dong-Han Kim

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/49572 ,  H01L23/3157 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A tape circuit substrate comprises a base film made of an insulating material, and a wiring pattern layer which is formed on the base film and has first leads that are connected to electrode pads arranged near a periphery of a semiconductor chip and second leads that are connected to electrode pads arranged near the center of the semiconductor chip. The semiconductor chip package comprises a semiconductor chip electrically bonded to the tape circuit substrate through chip bumps. In such a case, each of the leads is configured such that a tip end thereof to be bonded to the electrode pad has a width larger than that of a body portion thereof. According to the present invention, since the interval between the lead and the electrode pad can be made even narrower, a fine pitch semiconductor device can be realized.

Abstract translation: 带状电路基板包括由绝缘材料制成的基膜和形成在基膜上的布线图案层，并且具有连接到布置在半导体芯片的周围附近的电极焊盘的第一引线和连接的第二引线 到布置在半导体芯片的中心附近的电极焊盘。 半导体芯片封装包括通过芯片凸块电连接到带电路基板的半导体芯片。 在这种情况下，每个引线被构造成使得其与电极焊盘接合的前端的宽度大于其主体部分的宽度。 根据本发明，由于可以使引线与电极焊盘之间的间隔更窄，所以可以实现精细的间距半导体器件。

公开(公告)号：US07115483B2

公开(公告)日：2006-10-03

申请号：US10962591

申请日：2004-10-13

Applicant: Yong Hwan Kwon ,  Se Yong Oh ,  Sa Yoon Kang

Inventor： Yong Hwan Kwon ,  Se Yong Oh ,  Sa Yoon Kang

IPC: H01L21/00 ,  H01L21/44 ,  H01L21/30 ,  H01L23/02

CPC classification number: H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked chip package includes a substrate having an upper surface and a lower surface, a first semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the first semiconductor chip is attached to the upper surface of the substrate and the upper surface of the first semiconductor chip includes a plurality of first electrode pads, and a second semiconductor chip having an upper surface and a lower surface. The lower surface of the second semiconductor chip is attached to the upper surface of the first semiconductor chip, and the lower surface of the second semiconductor chip includes trenches that correspond to the locations of the first electrode pads on the upper surface of the first semiconductor chip.

公开(公告)号：US07109575B2

公开(公告)日：2006-09-19

申请号：US10862337

申请日：2004-06-08

Applicant: Sa-Yoon Kang ,  Dong-Han Kim ,  Ye-Chung Chung

Inventor： Sa-Yoon Kang ,  Dong-Han Kim ,  Ye-Chung Chung

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/12 ,  H01L23/52 ,  H01L29/40

CPC classification number: G02F1/13452 ,  H01L23/5387 ,  H01L2224/16 ,  H01L2924/07811 ,  H05K1/118 ,  H05K1/147 ,  H05K2201/068 ,  H05K2201/10681 ,  H01L2924/00

Abstract: Provided are a flexible film package module and a method of manufacturing the same that can be adapted for manufacture at lower cost and/or to adapt the characteristics of the flexible film package module for specific applications. The lower-cost flexible film package module includes a tape film that combines both a first insulating substrate, typically formed from a higher-cost polyimide material, and a second insulating substrate, typically formed from an insulating material or materials that are less expensive and/or provide modified performance when compared with the first insulating material. Both the first and second substrates will include complementary circuit patterns that will be electrically and physically connected to allow the composite substrate to function as a unitary substrate. The first and second substrates will also include connection regions that may be adapted for connection to printed circuit boards and/or electronic devices such as liquid crystal displays.

Abstract translation: 提供了一种柔性膜封装模块及其制造方法，其可以适于以更低成本制造和/或适应特定应用的柔性膜封装模块的特性。 较低成本的柔性膜封装模块包括一个胶带，其将通常由较高成本的聚酰亚胺材料形成的第一绝缘基板和通常由绝缘材料形成的第二绝缘基板或较便宜的材料和/ 或者与第一绝缘材料相比提供改进的性能。 第一和第二基板都将包括互补的电路图案，其将被电和物理连接，以允许复合基板作为整体基板。 第一和第二基板还将包括可适于连接到印刷电路板和/或诸如液晶显示器的电子设备的连接区域。

公开(公告)号：US20060202334A1

公开(公告)日：2006-09-14

申请号：US11421680

申请日：2006-06-01

Applicant: Yong-Hwan KWON ,  Sa-Yoon Kang ,  Chung-Sun Lee

Inventor： Yong-Hwan KWON ,  Sa-Yoon Kang ,  Chung-Sun Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/11 ,  H01L23/3114 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Provided are a method of forming a bump whose upper surface is substantially flat and whose area can be enlarged in a uniform pad pitch to simplify mounting a liquid crystal display drive IC (LDI) and a semiconductor chip and a mount structure using the method to minimize a pad area inside the chip. Thus, the pad area on an edge of a conventional chip is minimized and the bump is formed in a substantially flat location inside the chip and an electrical connection between the pad and the bump is performed by a redistribution metal line.

Abstract translation: 提供了一种形成凸起的方法，该凸块的上表面基本上是平的，并且其面积可以以均匀的垫间距扩大，以简化安装液晶显示驱动IC（LDI）和半导体芯片以及使用该方法的安装结构 芯片内部的焊盘区域。 因此，传统芯片的边缘上的焊盘区域被最小化，并且凸块形成在芯片内部的基本上平坦的位置，并且焊盘和凸块之间的电连接由再分布金属线执行。

公开(公告)号：US20050110935A1

公开(公告)日：2005-05-26

申请号：US10947220

申请日：2004-09-23

Applicant: Dong-Han Kim ,  Sa-Yoon Kang

Inventor： Dong-Han Kim ,  Sa-Yoon Kang

IPC: H01L21/60 ,  G02F1/13 ,  G02F1/133 ,  G02F1/1343 ,  G02F1/1345 ,  G02F1/136 ,  H01L21/00 ,  H01L23/00 ,  H01L23/498 ,  H05K3/22 ,  H05K3/36

CPC classification number: G02F1/13452 ,  H01L23/4985 ,  H01L2224/16 ,  H05K3/222 ,  H05K3/361

Abstract: A semiconductor chip, a TCP on which the semiconductor chip may be mounted, and/or an LCD apparatus which may include the TCP may be reduced in size by reducing the circuit patterns which may pass through the base film and bypass patterns which may be formed in wiring patterns within the chip. The size and/or manufacturing costs of the TCP and LCD apparatus may be reduced by changing circuit patterns which may pass through the base film.

Abstract translation: 可以通过减少可能通过基膜的电路图案和可形成的旁路图案来减小可以包括TCP的半导体芯片，其上可以安装半导体芯片的TCP和/或可以包括TCP的LCD装置的尺寸 在芯片内的布线图案。 可以通过改变可能通过基膜的电路图案来减小TCP和LCD装置的尺寸和/或制造成本。

公开(公告)号：US20050082647A1

公开(公告)日：2005-04-21

申请号：US10949091

申请日：2004-09-23

Applicant: Si-Hoon Lee ,  Sa-Yoon Kang ,  Dong-Han Kim

Inventor： Si-Hoon Lee ,  Sa-Yoon Kang ,  Dong-Han Kim

IPC: H01L21/60 ,  H01L23/28 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/49572 ,  H01L23/3157 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A tape circuit substrate comprises a base film made of an insulating material, and a wiring pattern layer which is formed on the base film and has first leads that are connected to electrode pads arranged near a periphery of a semiconductor chip and second leads that are connected to electrode pads arranged near the center of the semiconductor chip. The semiconductor chip package comprises a semiconductor chip electrically bonded to the tape circuit substrate through chip bumps. In such a case, each of the leads is configured such that a tip end thereof to be bonded to the electrode pad has a width larger than that of a body portion thereof. According to the present invention, since the interval between the lead and the electrode pad can be made even narrower, a fine pitch semiconductor device can be realized.

Abstract translation: 带状电路基板包括由绝缘材料制成的基膜和形成在基膜上的布线图案层，并且具有连接到布置在半导体芯片的周围附近的电极焊盘的第一引线和连接的第二引线 到布置在半导体芯片的中心附近的电极焊盘。 半导体芯片封装包括通过芯片凸块电连接到带电路基板的半导体芯片。 在这种情况下，每个引线被构造成使得其与电极焊盘接合的前端的宽度大于其主体部分的宽度。 根据本发明，由于可以使引线与电极焊盘之间的间隔更窄，所以可以实现精细的间距半导体器件。

公开(公告)号：US06849802B2

公开(公告)日：2005-02-01

申请号：US10357376

申请日：2003-02-04

Applicant: Young Hee Song ,  Sa Yoon Kang ,  Min Young Son

Inventor： Young Hee Song ,  Sa Yoon Kang ,  Min Young Son

IPC: H01L25/18 ,  H01L21/60 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L23/02

CPC classification number: H01L25/0657 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24145 ,  H01L2224/48091 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/06589 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/00014

Abstract: A semiconductor chip has connection lines that are routed to the side surface from bump pads on the back surface of the chip. Such semiconductor chips are stacked on a circuit board to form a chip stack package while bumps are interposed between the bump pads of the lower chip and bonding pads of the upper chip. Further, an interconnecting member such as a conductive adhesive or a wiring board is applied to the side surfaces of the stacked chips such that the connection lines are connected to the interconnecting member. Therefore, the centrally disposed bonding pads of the chips are electrically connected to the circuit board through the bumps, the bump pad, the connection lines and the interconnecting member. The semiconductor chip may have heat dissipation part formed on the back surface. Methods of manufacturing the semiconductor chip and the chip stack package are also provided.

Abstract translation: 半导体芯片具有从芯片背表面上的凸块焊接到侧表面的连接线。 这样的半导体芯片堆叠在电路板上以形成芯片堆叠封装，同时将凸块插入下芯片的凸块焊盘和上芯片的焊盘之间。 此外，将诸如导电粘合剂或布线板的互连构件施加到堆叠芯片的侧表面，使得连接线连接到互连构件。 因此，芯片的集中设置的接合焊盘通过凸块，凸块焊盘，连接线和互连构件电连接到电路板。 半导体芯片可以具有形成在背面上的散热部。 还提供了制造半导体芯片和芯片堆叠封装的方法。