公开(公告)号：US08510940B2

公开(公告)日：2013-08-20

申请号：US12790417

申请日：2010-05-28

申请人： Min-Yao Chen ,  Mao-Chang Chuang ,  Ming-Chiang Lee ,  Chien-Hao Wang

发明人： Min-Yao Chen ,  Mao-Chang Chuang ,  Ming-Chiang Lee ,  Chien-Hao Wang

IPC分类号： H01K3/10

CPC分类号： H05K3/403 ,  C25D5/022 ,  H05K3/108 ,  H05K2201/09645 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of fabricating a multi-trace via substrate is disclosed. A substrate at least having a first surface and a hole is provided, wherein the hole has a hole wall. A first conductive layer is formed on the entire surface of the substrate and the hole wall. A photoresist layer applied over the entire surface of the first conductive layer is selectively patterned to define a plurality of laterally separated regions on the first conductive layer. A patterned photoresist layer is used as a mask and a second conductive layer substantially thicker than the first conductive layer is electroplated on the laterally separated regions. The patterned photoresist layer is removed. The portion of the first conductive layer not covered by the second conductive layer is substantially removed to form a plurality of laterally separated traces extended on the first surface and through the hole.

摘要翻译： 公开了一种制造多迹线通孔衬底的方法。 提供至少具有第一表面和孔的基底，其中孔具有孔壁。 在基板的整个表面和孔壁上形成第一导电层。 施加在第一导电层的整个表面上的光致抗蚀剂层被选择性地图案化以在第一导电层上限定多个横向分离的区域。 使用图案化的光致抗蚀剂层作为掩模，并且基本上比第一导电层厚的第二导电层电镀在横向分离的区域上。 去除图案化的光致抗蚀剂层。 未被第二导电层覆盖的第一导电层的部分被基本上去除，以形成在第一表面上延伸并穿过孔的多个横向分离的迹线。

公开(公告)号：US08416577B2

公开(公告)日：2013-04-09

申请号：US12691502

申请日：2010-01-21

申请人： Chien-Hao Wang ,  Ming-Chiang Lee

发明人： Chien-Hao Wang ,  Ming-Chiang Lee

IPC分类号： H05K1/00

CPC分类号： H05K3/4007 ,  H05K1/111 ,  H05K1/113 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/108 ,  H05K3/205 ,  H05K3/28 ,  H05K3/385 ,  H05K3/4682 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2203/0315

摘要： The present invention relates to a coreless substrate and a method for making the same. The method for making the coreless substrate includes: (a) providing a carrier and a first conductive layer, wherein the carrier has a first surface and a second surface, and the first conductive layer is disposed on the first surface of the carrier; (b) forming a first embedded circuit on the first conductive layer; (c) forming a first dielectric layer so as to cover the first embedded circuit; (d) removing the carrier; (e) removing part of the first conductive layer so as to form at least one first pad; and (f) forming a first solder mask so as to cover the first embedded circuit and the first dielectric layer and to expose the first pad. Therefore, the coreless substrate of the present invention has high density of layout and involves low manufacturing cost.

摘要翻译： 无芯基板及其制造方法技术领域本发明涉及无芯基板及其制造方法。 制造无芯基板的方法包括：（a）提供载体和第一导电层，其中载体具有第一表面和第二表面，并且第一导电层设置在载体的第一表面上; （b）在第一导电层上形成第一嵌入电路; （c）形成第一介电层以覆盖第一嵌入式电路; （d）清除载体; （e）去除所述第一导电层的一部分以便形成至少一个第一焊盘; 和（f）形成第一焊料掩模以覆盖第一嵌入电路和第一电介质层并露出第一焊盘。 因此，本发明的无芯基板具有高的布局密度，并且制造成本低。

公开(公告)号：US20120073871A1

公开(公告)日：2012-03-29

申请号：US13307996

申请日：2011-11-30

申请人： Bernd Karl Appelt ,  Yuan-Chang Su ,  Ming-Chiang Lee ,  You-Lung Yen

发明人： Bernd Karl Appelt ,  Yuan-Chang Su ,  Ming-Chiang Lee ,  You-Lung Yen

IPC分类号： H05K1/11

CPC分类号： H05K3/0097 ,  H01L21/486 ,  H01L21/6835 ,  H01L2924/3025 ,  H05K3/28 ,  H05K3/427 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T156/1168 ,  Y10T428/24322

摘要： The present invention directs to double-sided multi-layered substrate a base, at least a through-hole passing through the base, patterned first and second metal layers formed on the two opposite surfaces of the base, and first and second plating layers. The first plating layer covers a sidewall of the through-hole and the bottom surface surrounding a bottom opening of the through hole. The second plating layer covers the first plating layer and the top surface surrounding a top opening of the through hole.

摘要翻译： 本发明涉及双面多层基板的基底，至少穿过基底的通孔，形成在基底的两个相对表面上的图案化的第一和第二金属层以及第一和第二镀层。 第一镀层覆盖通孔的侧壁和围绕通孔的底部开口的底面。 第二镀层覆盖第一镀层和围绕通孔的顶部开口的顶表面。

公开(公告)号：US20110260327A1

公开(公告)日：2011-10-27

申请号：US13173255

申请日：2011-06-30

申请人： Ming-Chiang Lee

发明人： Ming-Chiang Lee

IPC分类号： H01L23/48

CPC分类号： H01L21/568 ,  H01L23/3107 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00012

摘要： A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.

摘要翻译： 提供了包括第一图案化导电层，第二图案化导电层，芯片，接合线和模制化合物的四边形扁平非引线封装。 第一图案化导电层限定第一空间，并且第二图案化导电层限定第二空间，其中第一空间与第二空间重叠，并且第二图案化导电层的一部分围绕第二空间。 芯片设置在第二图案化导电层上。 接合线连接在芯片和第二图案化导电层之间。 模制化合物封装第二图案化导电层，芯片和接合线。 此外，还提供了制造四边形非铅包装的方法。

公开(公告)号：US20110174529A1

公开(公告)日：2011-07-21

申请号：US12790417

申请日：2010-05-28

申请人： Min-Yao CHEN ,  Mao-Chang Chuang ,  Ming-Chiang Lee ,  Chien-Hao Wang

发明人： Min-Yao CHEN ,  Mao-Chang Chuang ,  Ming-Chiang Lee ,  Chien-Hao Wang

IPC分类号： H05K1/11 ,  G03F7/20 ,  C25D5/02

CPC分类号： H05K3/403 ,  C25D5/022 ,  H05K3/108 ,  H05K2201/09645 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of fabricating a multi-trace via substrate is disclosed. A substrate at least having a first surface and a hole is provided, wherein the hole has a hole wall. A first conductive layer is formed on the entire surface of the substrate and the hole wall. A photoresist layer applied over the entire surface of the first conductive layer is selectively patterned to define a plurality of laterally separated regions on the first conductive layer. A patterned photoresist layer is used as a mask and a second conductive layer substantially thicker than the first conductive layer is electroplated on the laterally separated regions. The patterned photoresist layer is removed. The portion of the first conductive layer not covered by the second conductive layer is substantially removed to form a plurality of laterally separated traces extended on the first surface and through the hole.

摘要翻译： 公开了一种制造多迹线通孔衬底的方法。 提供至少具有第一表面和孔的基底，其中孔具有孔壁。 在基板的整个表面和孔壁上形成第一导电层。 施加在第一导电层的整个表面上的光致抗蚀剂层被选择性地图案化以在第一导电层上限定多个横向分离的区域。 使用图案化的光致抗蚀剂层作为掩模，并且基本上比第一导电层厚的第二导电层电镀在横向分离的区域上。 去除图案化的光致抗蚀剂层。 未被第二导电层覆盖的第一导电层的部分被基本上去除，以形成在第一表面上延伸并穿过孔的多个横向分离的迹线。

公开(公告)号：US20090087947A1

公开(公告)日：2009-04-02

申请号：US12237052

申请日：2008-09-24

申请人： Ho-Ming Tong ,  Shin-Hua Chao ,  Ming-Chiang Lee ,  Tai-Yuan Huang ,  Chao-Yuan Liu ,  Yung-Cheng Huang ,  Teck-Chong Lee ,  Jen-Chieh Kao ,  Jau-Shoung Chen

发明人： Ho-Ming Tong ,  Shin-Hua Chao ,  Ming-Chiang Lee ,  Tai-Yuan Huang ,  Chao-Yuan Liu ,  Yung-Cheng Huang ,  Teck-Chong Lee ,  Jen-Chieh Kao ,  Jau-Shoung Chen

IPC分类号： H01L21/00

CPC分类号： H01L21/561 ,  H01L21/4853 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： A flip chip package process is provided. First, a substrate strip including at least one substrate is provided. Next, at least one chip is disposed on the substrate, and the chip is electrically connected to the substrate. Then, a stencil having at least one opening and an air slot hole is disposed on an upper surface of the substrate strip, an air gap is formed between the stencil and the substrate strip, the air gap connects the opening and the air slot hole, and the chip is located in the opening. Finally, a liquid compound is formed into the opening of the stencil to encapsulate the chip, and a vacuum process is performed through the air slot hole and the air gap, so as to prevent the air inside the opening from being encapsulated by the liquid compound to become voids.

摘要翻译： 提供了一种倒装芯片封装工艺。 首先，提供包括至少一个基板的基板条。 接下来，在基板上设置至少一个芯片，并且芯片与基板电连接。 然后，具有至少一个开口和空气槽孔的模板设置在基板条的上表面上，在模板和基板条之间形成气隙，气隙连接开口和空气槽孔， 芯片位于开口处。 最后，将液体化合物形成在模板的开口中以封装芯片，并且通过空气槽孔和气隙进行真空处理，以防止开口内的空气被液体化合物包封 变成空洞。

公开(公告)号：US09406658B2

公开(公告)日：2016-08-02

申请号：US12972046

申请日：2010-12-17

申请人： Chun-Che Lee ,  Yuan-Chang Su ,  Ming Chiang Lee ,  Shih-Fu Huang

发明人： Chun-Che Lee ,  Yuan-Chang Su ,  Ming Chiang Lee ,  Shih-Fu Huang

IPC分类号： H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  H01L25/16 ,  H01L23/538 ,  H01L23/00

CPC分类号： H01L25/16 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/24 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

摘要： An embedded component device includes an electronic component including an electrical contact, an upper patterned conductive layer, a dielectric layer between the upper patterned conductive layer and the electronic component, a first electrical interconnect, a lower patterned conductive layer, a conductive via, and a second electrical interconnect. The dielectric layer has a first opening exposing the electrical contact, and a second opening extending from the lower patterned conductive layer to the upper patterned conductive layer. The first electrical interconnect extends from the electrical contact to the upper patterned conductive layer, and fills the first opening. The second opening has an upper portion exposing the upper patterned conductive layer and a lower portion exposing the lower patterned conductive layer. The conductive via is located at the lower portion of the second opening. The second electrical interconnect fills the upper portion of the second opening.

摘要翻译： 嵌入式组件装置包括电子部件，其包括电接触，上图案化导电层，上图案化导电层和电子部件之间的介电层，第一电互连，下图案化导电层，导电通孔和 第二电互连。 电介质层具有暴露电接触的第一开口和从下图案化导电层延伸到上图案化导电层的第二开口。 第一电互连从电接触延伸到上图案化导电层，并填充第一开口。 第二开口具有暴露上部图案化导电层的上部和暴露下部图案化导电层的下部。 导电通孔位于第二开口的下部。 第二电互连填充第二开口的上部。

公开(公告)号：US08372689B2

公开(公告)日：2013-02-12

申请号：US12691660

申请日：2010-01-21

申请人： Ming-Chiang Lee ,  Chien-Hao Wang

发明人： Ming-Chiang Lee ,  Chien-Hao Wang

IPC分类号： H01L21/00

CPC分类号： H01L23/5389 ,  H01L21/4846 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/82

摘要： In one embodiment, a method of forming a semiconductor device package includes: (1) providing a carrier and a semiconductor device including an active surface; (2) forming a first redistribution structure including a first electrical interconnect extending laterally within the first structure and a plurality of second electrical interconnects extending vertically from a first surface of the first interconnect, each second interconnect including a lower surface adjacent to the first surface and an upper surface opposite the lower surface; (3) disposing the device on the carrier such that the active surface is adjacent to the carrier; (4) disposing the first structure on the carrier such that the upper surface of each second interconnect is adjacent to the carrier, and the second interconnects are positioned around the device; and (5) forming a second redistribution structure adjacent to the active surface, and including a third electrical interconnect extending laterally within the second structure.

摘要翻译： 在一个实施例中，形成半导体器件封装的方法包括：（1）提供载体和包括活性表面的半导体器件; （2）形成第一再分配结构，其包括在第一结构内横向延伸的第一电互连和从第一互连的第一表面垂直延伸的多个第二电互连，每个第二互连包括与第一表面相邻的下表面， 与下表面相对的上表面; （3）将所述装置设置在所述载体上使得所述活性表面与所述载体相邻; （4）将所述第一结构设置在所述载体上，使得每个第二互连件的上表面与所述载体相邻，并且所述第二互连件围绕所述装置定位; 和（5）形成与活性表面相邻的第二再分布结构，并且包括在第二结构内横向延伸的第三电互连。

公开(公告)号：US08288869B2

公开(公告)日：2012-10-16

申请号：US12779818

申请日：2010-05-13

申请人： Shih-Fu Huang ,  Yuan-Chang Su ,  Chia-Cheng Chen ,  Kuang-Hsiung Chen ,  Ming-Chiang Lee ,  Bernd Karl Appelt ,  Chia-Hsiung Hsieh

发明人： Shih-Fu Huang ,  Yuan-Chang Su ,  Chia-Cheng Chen ,  Kuang-Hsiung Chen ,  Ming-Chiang Lee ,  Bernd Karl Appelt ,  Chia-Hsiung Hsieh

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/145 ,  H01L24/16 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die.

摘要翻译： 半导体封装包括基板，管芯和封装体。 基材包括：（a）包含用纤维增强的树脂的芯; （b）延伸穿过所述芯的多个开口; （c）电介质层; 和（d）设置在电介质层和芯之间的单个导电层。 单个导电层的下表面的一部分覆盖多个开口以形成多个用于半导体封装外部电连接的第一接触焊盘。 单个导电层的上表面的暴露部分形成多个第二接触焊盘。 模具电连接到多个第二接触焊盘，并且封装体封装模具。

公开(公告)号：US20100206618A1

公开(公告)日：2010-08-19

申请号：US12691502

申请日：2010-01-21

申请人： Chien-Hao Wang ,  Ming-Chiang Lee

发明人： Chien-Hao Wang ,  Ming-Chiang Lee

IPC分类号： H05K1/09 ,  H05K3/00 ,  C23C28/00

CPC分类号： H05K3/4007 ,  H05K1/111 ,  H05K1/113 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/108 ,  H05K3/205 ,  H05K3/28 ,  H05K3/385 ,  H05K3/4682 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2203/0315

摘要： The present invention relates to a coreless substrate and a method for making the same. The method for making the coreless substrate includes: (a) providing a carrier and a first conductive layer, wherein the carrier has a first surface and a second surface, and the first conductive layer is disposed on the first surface of the carrier; (b) forming a first embedded circuit on the first conductive layer; (c) forming a first dielectric layer so as to cover the first embedded circuit; (d) removing the carrier; (e) removing part of the first conductive layer so as to form at least one first pad; and (f) forming a first solder mask so as to cover the first embedded circuit and the first dielectric layer and to expose the first pad. Therefore, the coreless substrate of the present invention has high density of layout and involves low manufacturing cost.

摘要翻译： 无芯基板及其制造方法技术领域本发明涉及无芯基板及其制造方法。 制造无芯基板的方法包括：（a）提供载体和第一导电层，其中载体具有第一表面和第二表面，并且第一导电层设置在载体的第一表面上; （b）在第一导电层上形成第一嵌入电路; （c）形成第一介电层以覆盖第一嵌入式电路; （d）清除载体; （e）去除所述第一导电层的一部分以便形成至少一个第一焊盘; 和（f）形成第一焊料掩模以覆盖第一嵌入电路和第一电介质层并露出第一焊盘。 因此，本发明的无芯基板具有高的布局密度，并且制造成本低。