公开(公告)号：US20110169150A1

公开(公告)日：2011-07-14

申请号：US13006340

申请日：2011-01-13

申请人： Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Ming Chiang Lee ,  Bernd Karl Appelt

发明人： Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Ming Chiang Lee ,  Bernd Karl Appelt

IPC分类号： H01L23/495 ,  H01L21/60 ,  H05K3/10

CPC分类号： H01L24/14 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/49155 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity.

摘要翻译： 半导体封装包括基板单元，与第一接触焊盘电连接的管芯，以及覆盖第一图案化导电层和管芯的封装体。 基板单元包括：（1）第一图案化导电层; （2）暴露第一图案化导电层的一部分以形成第一接触焊盘的第一电介质层; （3）第二图案化导电层; （4）限定从第一图案化导电层延伸到第二图案化导电层的开口的第二介电层，其中第二图案化导电层包括由第二介电层暴露的第二接触焊盘; 和（5）通过开口从第一图案化导电层延伸到第二接触垫的导电柱，每个导电柱填充相应的一个开口。 导电柱中的至少一个限定了空腔。

公开(公告)号：US08569894B2

公开(公告)日：2013-10-29

申请号：US13006340

申请日：2011-01-13

申请人： Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Ming Chiang Lee ,  Bernd Karl Appelt

发明人： Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Ming Chiang Lee ,  Bernd Karl Appelt

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/14 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/49155 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity.

摘要翻译： 半导体封装包括基板单元，与第一接触焊盘电连接的管芯，以及覆盖第一图案化导电层和管芯的封装体。 基板单元包括：（1）第一图案化导电层; （2）暴露第一图案化导电层的一部分以形成第一接触焊盘的第一电介质层; （3）第二图案化导电层; （4）限定从第一图案化导电层延伸到第二图案化导电层的开口的第二介电层，其中第二图案化导电层包括由第二介电层暴露的第二接触焊盘; 和（5）通过开口从第一图案化导电层延伸到第二接触垫的导电柱，每个导电柱填充相应的一个开口。 导电柱中的至少一个限定了空腔。

公开(公告)号：US08786062B2

公开(公告)日：2014-07-22

申请号：US12904799

申请日：2010-10-14

申请人： Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Chia-Hsiung Hsieh ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh

发明人： Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Chia-Hsiung Hsieh ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh

IPC分类号： H01L21/683 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/3128 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/27013 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.

摘要翻译： 包装载体包括：（a）限定多个开口的电介质层; （b）图案化的导电层，嵌入在介电层中并邻近介质层的第一表面设置; 多个导电柱，设置在相应的一个开口中，其中开口在介电层的第二表面与图案化的导电层之间延伸，导电柱a连接到图案化的导电层，端部 每个导电柱具有弯曲轮廓并且背离图案化的导电层; 和（d）图案化的阻焊层，邻近电介质层的第一表面设置并暴露与接触焊盘对应的图案化导电层的部分。 半导体封装包括封装载体，芯片和覆盖芯片和封装载体的密封剂。

公开(公告)号：US08288869B2

公开(公告)日：2012-10-16

申请号：US12779818

申请日：2010-05-13

申请人： Shih-Fu Huang ,  Yuan-Chang Su ,  Chia-Cheng Chen ,  Kuang-Hsiung Chen ,  Ming-Chiang Lee ,  Bernd Karl Appelt ,  Chia-Hsiung Hsieh

发明人： Shih-Fu Huang ,  Yuan-Chang Su ,  Chia-Cheng Chen ,  Kuang-Hsiung Chen ,  Ming-Chiang Lee ,  Bernd Karl Appelt ,  Chia-Hsiung Hsieh

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/145 ,  H01L24/16 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die.

摘要翻译： 半导体封装包括基板，管芯和封装体。 基材包括：（a）包含用纤维增强的树脂的芯; （b）延伸穿过所述芯的多个开口; （c）电介质层; 和（d）设置在电介质层和芯之间的单个导电层。 单个导电层的下表面的一部分覆盖多个开口以形成多个用于半导体封装外部电连接的第一接触焊盘。 单个导电层的上表面的暴露部分形成多个第二接触焊盘。 模具电连接到多个第二接触焊盘，并且封装体封装模具。

公开(公告)号：US08330267B2

公开(公告)日：2012-12-11

申请号：US12607405

申请日：2009-10-28

申请人： Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Yuan-Chang Su ,  Shih-Fu Huang ,  Bernd Karl Appelt

发明人： Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Yuan-Chang Su ,  Shih-Fu Huang ,  Bernd Karl Appelt

IPC分类号： H01L23/04

CPC分类号： H01L23/49816 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/28 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires.

摘要翻译： 半导体封装包括图案化金属箔，芯片，电线，图案化电介质层，粘合剂层和模塑料。 图案化金属箔具有与其相对的第一表面和第二表面。 图案化的电介质层设置在第二表面上并且具有暴露图案化金属箔的至少一部分的开口以形成用于外部电连接的接头。 芯片设置在第一表面上。 粘合剂层设置在芯片和图案化的金属箔之间。 导线分别连接芯片和图案化金属箔。 图案化电介质层位于电线和图案化金属箔之间的交叉点下方。 图案化电介质层，导线和图案化金属箔在平面上彼此重叠。 模塑料配置在第一表面上并覆盖芯片和电线。

公开(公告)号：US20110057301A1

公开(公告)日：2011-03-10

申请号：US12607405

申请日：2009-10-28

申请人： Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Yuan-Chang Su ,  Shih-Fu Huang ,  Bernd Karl Appelt

发明人： Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Yuan-Chang Su ,  Shih-Fu Huang ,  Bernd Karl Appelt

IPC分类号： H01L23/488

CPC分类号： H01L23/49816 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/28 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires.

摘要翻译： 半导体封装包括图案化金属箔，芯片，电线，图案化电介质层，粘合剂层和模塑料。 图案化金属箔具有与其相对的第一表面和第二表面。 图案化的电介质层设置在第二表面上并且具有暴露图案化金属箔的至少一部分的开口以形成用于外部电连接的接头。 芯片设置在第一表面上。 粘合剂层设置在芯片和图案化的金属箔之间。 导线分别连接芯片和图案化金属箔。 图案化电介质层位于电线和图案化金属箔之间的交叉点下方。 图案化电介质层，导线和图案化金属箔在平面上彼此重叠。 模塑料配置在第一表面上并覆盖芯片和电线。

公开(公告)号：US08399776B2

公开(公告)日：2013-03-19

申请号：US12562950

申请日：2009-09-18

申请人： Bernd Karl Appelt ,  William T Chen ,  Calvin Cheung ,  Shih-Fu Huang ,  Yuan-Chang Su ,  Chia-Cheng Chen ,  Ta-Chun Lee

发明人： Bernd Karl Appelt ,  William T Chen ,  Calvin Cheung ,  Shih-Fu Huang ,  Yuan-Chang Su ,  Chia-Cheng Chen ,  Ta-Chun Lee

IPC分类号： H05K1/09

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/498 ,  H01L24/12 ,  H01L24/16 ,  H01L24/28 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85664 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/00

摘要： A substrate having single patterned metal layer includes a patterned base having at least a plurality of apertures, the patterned metal layer disposed on the patterned base, and a first surface finish layer. Parts of the lower surface of the patterned metal layer are exposed by the apertures of the patterned base to form a plurality of first contact pads for downward electrical connection externally, and parts of the upper surface of the patterned metal layer function as a plurality of second contact pads for upward electrical connection externally. The first surface finish layer is disposed at least on one or more surfaces of the second contact pads, and the first surface finish layer is wider than the second contact pad beneath. A package applied with the substrate disclosed herein further comprises at least a die conductively connected to the second contact pads of the substrate.

摘要翻译： 具有单一图案化金属层的衬底包括具有至少多个孔的图案化基底，设置在图案化基底上的图案化金属层和第一表面光洁度层。 图案化金属层的下表面的部分由图案化基底的孔暴露以形成用于向外电连接的多个第一接触焊盘，并且图案化金属层的上表面的一部分用作多个第二 接触垫用于向外电连接。 第一表面光洁度层设置在第二接触垫的至少一个或多个表面上，并且第一表面光洁度层比下面的第二接触垫宽。 施加有本文公开的衬底的封装还包括至少一个导体连接到衬底的第二接触焊盘的管芯。

公开(公告)号：US08284561B2

公开(公告)日：2012-10-09

申请号：US12850872

申请日：2010-08-05

申请人： Yuan-Chang Su ,  Shih-Fu Huang ,  Bernd Karl Appelt ,  Ming-Chiang Lee

发明人： Yuan-Chang Su ,  Shih-Fu Huang ,  Bernd Karl Appelt ,  Ming-Chiang Lee

IPC分类号： H05K1/18 ,  H05K1/11

CPC分类号： H05K1/186 ,  H01L2224/16225 ,  H01L2924/15153 ,  H01L2924/15321 ,  H05K3/0097 ,  H05K3/4697 ,  H05K2201/0352 ,  H05K2203/1536 ,  Y10T29/4913 ,  Y10T29/49165

摘要： The present invention directs to fabrication methods of the embedded component package structures by providing preformed lamination structures, joining or stacking the preformed laminate structures and mounting at least one electronic component to the joined structures. By way of the fabrication methods, the production yield can be greatly improved with lower cycle time.

摘要翻译： 本发明通过提供预制的层压结构，连接或堆叠预成型的层压结构并将至少一个电子部件安装到接合的结构来指导嵌入式组件封装结构的制造方法。 通过制造方法，可以以较低的循环时间大大提高生产产量。

公开(公告)号：US20120033394A1

公开(公告)日：2012-02-09

申请号：US12850872

申请日：2010-08-05

申请人： Yuan-Chang Su ,  Shih-Fu Huang ,  Bernd Karl Appelt ,  Ming-Chiang Lee

发明人： Yuan-Chang Su ,  Shih-Fu Huang ,  Bernd Karl Appelt ,  Ming-Chiang Lee

IPC分类号： H05K7/10 ,  H05K3/42 ,  H05K3/30

CPC分类号： H05K1/186 ,  H01L2224/16225 ,  H01L2924/15153 ,  H01L2924/15321 ,  H05K3/0097 ,  H05K3/4697 ,  H05K2201/0352 ,  H05K2203/1536 ,  Y10T29/4913 ,  Y10T29/49165

摘要： The present invention directs to fabrication methods of the embedded component package structures by providing preformed lamination structures, joining or stacking the preformed laminate structures and mounting at least one electronic component to the joined structures. By way of the fabrication methods, the production yield can be greatly improved with lower cycle time.

摘要翻译： 本发明通过提供预制的层压结构，连接或堆叠预成型的层压结构并将至少一个电子部件安装到接合的结构来指导嵌入式组件封装结构的制造方法。 通过制造方法，可以以较低的循环时间大大提高生产产量。

公开(公告)号：US08367473B2

公开(公告)日：2013-02-05

申请号：US12779800

申请日：2010-05-13

申请人： Shih-Fu Huang ,  Yuan-Chang Su ,  Chia-Cheng Chen ,  Ta-Chun Lee ,  Kuang-Hsiung Chen

发明人： Shih-Fu Huang ,  Yuan-Chang Su ,  Chia-Cheng Chen ,  Ta-Chun Lee ,  Kuang-Hsiung Chen

IPC分类号： H01L21/768 ,  H01L21/786

CPC分类号： H01L23/498 ,  H01L23/3121 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/27013 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48611 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48699 ,  H01L2224/48711 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48811 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/85411 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012

摘要： A chip package structure includes a substrate, a die, and a package body. The substrate includes a single patterned, electrically conductive layer, and a patterned dielectric layer adjacent to an upper surface of the electrically conductive layer. A part of a lower surface of the electrically conductive layer forms first contact pads for electrical connection externally. The patterned dielectric layer exposes a part of the upper surface of the electrically conductive layer to form second contact pads. The electrically conductive layer exposes the lower surface of the patterned dielectric layer on a lower periphery of the substrate. The die is electrically connected to the second contact pads, the patterned dielectric layer and the die being positioned on the same side of the electrically conductive layer. The package body is disposed adjacent to the upper surface of the electrically conductive layer and covers the patterned dielectric layer and the die.

摘要翻译： 芯片封装结构包括基板，管芯和封装体。 衬底包括单个图案化的导电层，以及与导电层的上表面相邻的图案化电介质层。 导电层的下表面的一部分形成用于外部电连接的第一接触垫。 图案化的电介质层暴露导电层的上表面的一部分以形成第二接触焊盘。 导电层在图案化介电层的下表面暴露在基底的下周边。 模具电连接到第二接触焊盘，图案化的介电层和管芯位于导电层的同一侧。 封装体靠近导电层的上表面设置并覆盖图案化的介电层和管芯。