公开(公告)号：US06881996B2

公开(公告)日：2005-04-19

申请号：US10935376

申请日：2004-09-07

申请人： Chun-Hon Chen ,  Ssu-Pin Ma ,  Ta-Hsun Yeh ,  Yen-Shih Ho ,  Kuo-Reay Peng ,  Heng-Ming Hsu ,  Kong-Beng Thei ,  Chi-Wu Chou

发明人： Chun-Hon Chen ,  Ssu-Pin Ma ,  Ta-Hsun Yeh ,  Yen-Shih Ho ,  Kuo-Reay Peng ,  Heng-Ming Hsu ,  Kong-Beng Thei ,  Chi-Wu Chou

IPC分类号： H01L21/02 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/08 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal-insulator-metal (MIM) capacitor structure and method of fabrication for CMOS circuits having copper interconnections are described. The method provides metal capacitors with high figure of merit Q (Xc/R) and which does not require additional masks and metal layers. The method forms a copper capacitor bottom metal (CBM) electrode while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si3N4) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer is used to protect the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.

摘要翻译： 描述了具有铜互连的CMOS电路的金属绝缘体金属（MIM）电容器结构和制造方法。 该方法提供具有高品质因数Q（X / C / R）的金属电容器，并且不需要额外的掩模和金属层。 该方法形成铜电容器底部金属（CBM）电极，同时通过镶嵌工艺形成焊盘触点和铜互连水平。 在铜上形成绝缘（Si 3 N 4 N 4）金属保护层，形成电容器电极间电介质层。 使用金属保护缓冲器来保护薄的电极间层，并且蚀刻开口以焊接触点和互连线。 沉积并图案化TiN / AlCu / TiN金属层以形成电容器顶部金属（CTM）电极，下一级互连，并在铜焊盘触点上提供焊盘保护层。 厚TiN / AlCu / TiN CTM电极降低了电容器串联电阻，提高了电容器的品质因数Q，而焊盘保护层保护铜免受腐蚀。

公开(公告)号：US06472721B2

公开(公告)日：2002-10-29

申请号：US09963749

申请日：2001-09-27

申请人： Ssu-Pin Ma ,  Chun-Hon Chen ,  Ta-Hsun Yeh ,  Kuo-Reay Peng ,  Heng-Ming Hsu ,  Kong-Beng Thei ,  Chi-Wu Chou ,  Yen-Shih Ho

发明人： Ssu-Pin Ma ,  Chun-Hon Chen ,  Ta-Hsun Yeh ,  Kuo-Reay Peng ,  Heng-Ming Hsu ,  Kong-Beng Thei ,  Chi-Wu Chou ,  Yen-Shih Ho

IPC分类号： H01L2943

CPC分类号： H01L28/40 ,  H01L21/3212 ,  H01L21/76838 ,  H01L28/56 ,  H01L28/60 ,  H01L28/90

摘要： In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.

摘要翻译： 在许多混合信号或射频Rf应用中，同时需要电感器和电容器。 对于高性能电感器件，需要厚金属层来提高性能，通常需要额外的掩模工艺。 本发明同时描述了铜金属 - 绝缘体 - 金属（MIM）电容器和厚金属​​电感器的结构和方法，同时仅使用一个掩模用于大马士革中的高频混合信号或Rf，CMOS应用， 双镶嵌沟/通孔工艺。 本发明形成的高性能器件结构包括：平行电容器底部金属（CBM）电极和电容器顶部金属（CTM）电极，金属 - 绝缘体 - 金属（MIM）电容器，厚电感器金属布线，互连和接触通孔。

公开(公告)号：US06329234B1

公开(公告)日：2001-12-11

申请号：US09624026

申请日：2000-07-24

申请人： Ssu-Pin Ma ,  Chun-Hon Chen ,  Ta-Hsun Yeh ,  Kuo-Reay Peng ,  Heng-Ming Hsu ,  Kong-Beng Thei ,  Chi-Wu Chou ,  Yen-Shih Ho

发明人： Ssu-Pin Ma ,  Chun-Hon Chen ,  Ta-Hsun Yeh ,  Kuo-Reay Peng ,  Heng-Ming Hsu ,  Kong-Beng Thei ,  Chi-Wu Chou ,  Yen-Shih Ho

IPC分类号： H01L218238

CPC分类号： H01L28/40 ,  H01L21/3212 ,  H01L21/76838 ,  H01L28/56 ,  H01L28/60 ,  H01L28/90

摘要： In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.

摘要翻译： 在许多混合信号或射频Rf应用中，同时需要电感器和电容器。 对于高性能电感器件，需要厚金属层来提高性能，通常需要额外的掩模工艺。 本发明同时描述了铜金属 - 绝缘体 - 金属（MIM）电容器和厚金属​​电感器的结构和方法，同时仅使用一个掩模用于大马士革中的高频混合信号或Rf，CMOS应用， 双镶嵌沟/通孔工艺。 本发明形成的高性能器件结构包括：平行电容器底部金属（CBM）电极和电容器顶部金属（CTM）电极，金属 - 绝缘体 - 金属（MIM）电容器，厚电感器金属布线，互连和接触通孔。

公开(公告)号：US07038294B2

公开(公告)日：2006-05-02

申请号：US09821521

申请日：2001-03-29

申请人： Ssu-Pin Ma ,  Yen-Shih Ho

发明人： Ssu-Pin Ma ,  Yen-Shih Ho

IPC分类号： H01L29/00

CPC分类号： H01L24/05 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/30105 ,  H01L2924/30107 ,  Y10S257/909 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2224/48744

摘要： Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a spirally patterned conductor layer which terminates in a microelectronic structure within the center of the spirally patterned conductor layer. The spirally patterned conductor layer forms a planar spiral inductor, and the microelectronic structure formed within the center of the spirally patterned conductor layer further comprises a series of electrically interconnected sub-patterns. The method contemplates a microelectronic fabrication fabricated in accord with the method. The microelectronic fabrication is fabricated with optimal performance while occupying minimal microelectronic substrate area.

公开(公告)号：US20050029566A1

公开(公告)日：2005-02-10

申请号：US10935376

申请日：2004-09-07

申请人： Chun-Hon Chen ,  Ssu-Pin Ma ,  Ta-Hsun Yeh ,  Yen-Shih Ho ,  Kuo-Reay Peng ,  Heng-Ming Hsu ,  Kong-Beng Thei ,  Chi-Wu Chou

发明人： Chun-Hon Chen ,  Ssu-Pin Ma ,  Ta-Hsun Yeh ,  Yen-Shih Ho ,  Kuo-Reay Peng ,  Heng-Ming Hsu ,  Kong-Beng Thei ,  Chi-Wu Chou

IPC分类号： H01L21/02 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/08 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal-insulator-metal (MIM) capacitor structure and method of fabrication for CMOS circuits having copper interconnections are described. The method provides metal capacitors with high figure of merit Q (Xc/R) and which does not require additional masks and metal layers. The method forms a copper capacitor bottom metal (CBM) electrode while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si3N4) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer is used to protect the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.

摘要翻译： 描述了具有铜互连的CMOS电路的金属绝缘体金属（MIM）电容器结构和制造方法。 该方法提供具有高品质因数Q（Xc / R）的金属电容器，并且不需要额外的掩模和金属层。 该方法形成铜电容器底部金属（CBM）电极，同时通过镶嵌工艺形成焊盘触点和铜互连水平。 在铜上形成绝缘（Si3N4）金属保护层，形成电容器电极间电介质层。 使用金属保护缓冲器来保护薄的电极间层，并且蚀刻开口以焊接触点和互连线。 沉积并图案化TiN / AlCu / TiN金属层以形成电容器顶部金属（CTM）电极，下一级互连，并在铜焊盘触点上提供焊盘保护层。 厚TiN / AlCu / TiN CTM电极降低了电容器串联电阻，提高了电容器的品质因数Q，而焊盘保护层保护铜免受腐蚀。

公开(公告)号：US06812088B1

公开(公告)日：2004-11-02

申请号：US10167856

申请日：2002-06-11

申请人： Chun-Hon Chen ,  Ssu-Pin Ma ,  Ta-Hsun Yeh ,  Yen-Shih Ho ,  Kuo-Reay Peng ,  Heng-Ming Hsu ,  Kong-Beng Thei ,  Chi-Wu Chou

发明人： Chun-Hon Chen ,  Ssu-Pin Ma ,  Ta-Hsun Yeh ,  Yen-Shih Ho ,  Kuo-Reay Peng ,  Heng-Ming Hsu ,  Kong-Beng Thei ,  Chi-Wu Chou

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： This MIM structure provides metal capacitors with high figure of merit Q (Xc/R) and does not require additional masks and metal layers. A copper capacitor bottom metal (CBM) electrode is formed, while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si3N4) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer protects the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.

摘要翻译： 该MIM结构提供具有高品质因数Q（Xc / R）的金属电容器，并且不需要额外的掩模和金属层。 形成铜电容器底部金属（CBM）电极，同时通过镶嵌工艺同时形成焊盘触点和铜互连水平。 在铜上形成绝缘（Si3N4）金属保护层，形成电容器电极间电介质层。 金属保护缓冲器保护薄的电极间层，并且蚀刻开口以焊接触点和互连线。 沉积并图案化TiN / AlCu / TiN金属层以形成电容器顶部金属（CTM）电极，下一级互连，并在铜焊盘触点上提供焊盘保护层。 厚TiN / AlCu / TiN CTM电极降低了电容器串联电阻，提高了电容器的品质因数Q，而焊盘保护层保护铜免受腐蚀。

公开(公告)号：US06667217B1

公开(公告)日：2003-12-23

申请号：US09795115

申请日：2001-03-01

申请人： Heng-Ming Hsu ,  Jau-Yuann Chung ,  Yen-Shih Ho ,  Chun-Hon Chen ,  Kuo-Reay Peng ,  Ta-Hsun Yeh ,  Kong-Beng Thei ,  Ssu-Pin Ma

发明人： Heng-Ming Hsu ,  Jau-Yuann Chung ,  Yen-Shih Ho ,  Chun-Hon Chen ,  Kuo-Reay Peng ,  Ta-Hsun Yeh ,  Kong-Beng Thei ,  Ssu-Pin Ma

IPC分类号： H01L2120

CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01F41/042 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A process for integrating the fabrication of a thick, copper inductor structure, with the fabrication of narrow channel length CMOS devices, has been developed. The integrated process features the use of only one additional photolithographic masking step, used to form the opening in an IMD layer, that will accommodate the subsequent inductor structure. After forming damascene type openings in the same IMD layer, in the CMOS region, copper is deposited and then defined, to result in a thick, copper inductor structure, in the opening in the IMD layer, in a first region of a semiconductor substrate, as well as to result in copper interconnect structures, in the damascene type openings located in a second region of the semiconductor structure, used for the narrow channel length CMOS devices. The use of a thick, copper inductor structure, equal to the thickness of the IMD layer, results in increased inductance, or an increased quality factor, when compared to counterparts formed with thinner metal inductors.

摘要翻译： 已经开发了将厚铜电感器结构的制造与窄沟道长度CMOS器件的制造相结合的工艺。 集成过程的特征在于仅使用一个额外的光刻掩模步骤，用于在IMD层中形成开口，其将适应随后的电感器结构。 在相同的IMD层中形成镶嵌型开口之后，在CMOS区域中，沉积铜，然后限定铜，以在半导体衬底的第一区域中的IMD层的开口中产生厚的铜电感器结构， 以及在半导体结构的第二区域中的镶嵌型开口中产生用于窄沟道长度CMOS器件的铜互连结构。 与使用较薄的金属电感器形成的对应物相比，使用等于IMD层的厚度的厚铜电感器结构导致增加的电感或增加的品质因数。

公开(公告)号：US08673686B2

公开(公告)日：2014-03-18

申请号：US13492649

申请日：2012-06-08

申请人： Hung-Jen Lee ,  Shu-Ming Chang ,  Chen-Han Chiang ,  Tsang-Yu Liu ,  Yen-Shih Ho

发明人： Hung-Jen Lee ,  Shu-Ming Chang ,  Chen-Han Chiang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC分类号： H01L21/44

CPC分类号： H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

摘要： An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defining a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively, a cutting support structure located on peripheries of the chip support rings, a plurality of stop rings surrounding the chip support rings respectively, wherein a gap pattern separating the stop rings from the cutting support structure and the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

摘要翻译： 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定多个器件区域的多个预定划线的第一衬底; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环，位于芯片支撑环的周边的切割支撑结构，围绕 所述芯片支撑环分别具有将所述止动环与所述切割支撑结构和所述芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。

公开(公告)号：US08409925B2

公开(公告)日：2013-04-02

申请号：US13178375

申请日：2011-07-07

申请人： Hung-Jen Lee ,  Shu-Ming Chang ,  Chen-Han Chiang ,  Tsang-Yu Liu ,  Yen-Shih Ho

发明人： Hung-Jen Lee ,  Shu-Ming Chang ,  Chen-Han Chiang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC分类号： H01L21/00

CPC分类号： H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

摘要： An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

公开(公告)号：US07592891B2

公开(公告)日：2009-09-22

申请号：US12079059

申请日：2008-03-24

申请人： Hun-Ming Hsu ,  Yen-Shih Ho

发明人： Hun-Ming Hsu ,  Yen-Shih Ho

IPC分类号： H01F5/00

CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F41/041 ,  H01F2017/0046 ,  H01L2924/0002 ,  Y10T29/4902 ,  Y10T29/49062 ,  Y10T29/49073 ,  H01L2924/00

摘要： Within a method for fabricating an inductor structure there is first provided a substrate. There is then formed over the substrate a planar spiral conductor layer to form a planar spiral inductor, wherein a successive series of spirals within the planar spiral conductor layer is formed with a variation in at least one of: (1) a series of linewidths of the successive series of spirals; and (2) a series of spacings of the successive series of spirals. The method contemplates a planar spiral inductor structure fabricated in accord with the method. A planar spiral inductor structure fabricated in accord with the method is characterized by an enhanced Q value of the planar spiral inductor structure.

摘要翻译： 在制造电感器结构的方法中，首先提供衬底。 然后在基板上形成平面螺旋导体层以形成平面螺旋形电感器，其中平面螺旋导体层内的连续的一系列螺旋形成为以下至少之一的变化：（1）一系列线宽 连续的一系列螺旋; 和（2）连续的螺旋系列的一系列间距。 该方法考虑了根据该方法制造的平面螺旋电感器结构。 根据该方法制造的平面螺旋电感器结构的特征在于平面螺旋电感器结构的增强的Q值。