公开(公告)号：US11848176B2

公开(公告)日：2023-12-19

申请号：US17315234

申请日：2021-05-07

Applicant: Applied Materials, Inc.

Inventor： Leonid Dorf ,  Rajinder Dhindsa ,  James Rogers ,  Daniel Sang Byun ,  Evgeny Kamenetskiy ,  Yue Guo ,  Kartik Ramaswamy ,  Valentin N. Todorow ,  Olivier Luere

IPC: H01J37/32 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/683

CPC classification number: H01J37/32128 ,  H01J37/32146 ,  H01J37/32174 ,  H01J37/32183 ,  H01J37/32568 ,  H01J37/32577 ,  H01J37/32715 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/6831 ,  H01J2237/2007 ,  H01J2237/3321 ,  H01J2237/3341

Abstract: Embodiments of the disclosure provided herein include an apparatus and method for the plasma processing of a substrate in a processing chamber. More specifically, embodiments of this disclosure describe a biasing scheme that is configured to provide a radio frequency (RF) generated RF waveform from an RF generator to one or more electrodes within a processing chamber and a pulsed-voltage (PV) waveform delivered from one or more pulsed-voltage (PV) generators to the one or more electrodes within the processing chamber. The plasma process(es) disclosed herein can be used to control the shape of an ion energy distribution function (IEDF) and the interaction of the plasma with a surface of a substrate during plasma processing.

公开(公告)号：US11728124B2

公开(公告)日：2023-08-15

申请号：US17377639

申请日：2021-07-16

Applicant: APPLIED MATERIALS, INC.

Inventor： Leonid Dorf ,  Travis Koh ,  Olivier Luere ,  Olivier Joubert ,  Philip A. Kraus ,  Rajinder Dhindsa ,  James Rogers

IPC: H01J37/08 ,  H01J37/248 ,  H01J37/32

CPC classification number: H01J37/08 ,  H01J37/248 ,  H01J37/32577 ,  H01J37/32706 ,  H01J37/32715

Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse-bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.

公开(公告)号：US20150214066A1

公开(公告)日：2015-07-30

申请号：US14164679

申请日：2014-01-27

Applicant: Applied Materials, Inc.

Inventor： Olivier Luere ,  Srinivas D. Nemani ,  Sean S. Kang

IPC: H01L21/311 ,  H01L21/033

CPC classification number: H01L21/02063 ,  H01J37/32082 ,  H01J37/32192 ,  H01J37/32357 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/76802 ,  H01L2221/1063

Abstract: Embodiments of the technology include a semiconductor patterning method. The method may include forming a layer of masking material on regions of dielectric material above a semiconductor substrate. The method may include forming a trench through the masking material. This transformation may expose at least a portion of the dielectric material. The method may include forming a protective layer over the exposed portion of the dielectric material. The method may involve removing the masking material from the semiconductor substrate.

Abstract translation: 该技术的实施例包括半导体图案化方法。 该方法可以包括在半导体衬底上方的电介质材料的区域上形成掩模材料层。 该方法可以包括通过掩模材料形成沟槽。 该变换可以暴露电介质材料的至少一部分。 该方法可以包括在介电材料的暴露部分上形成保护层。 该方法可以包括从半导体衬底去除掩模材料。

公开(公告)号：US12237148B2

公开(公告)日：2025-02-25

申请号：US18375886

申请日：2023-10-02

Applicant: Applied Materials, Inc.

Inventor： Leonid Dorf ,  Rajinder Dhindsa ,  James Rogers ,  Daniel Sang Byun ,  Evgeny Kamenetskiy ,  Yue Guo ,  Kartik Ramaswamy ,  Valentin N. Todorow ,  Olivier Luere ,  Linying Cui

IPC: H01J37/32 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/683

Abstract: Embodiments of the disclosure provided herein include an apparatus and method for the plasma processing of a substrate in a processing chamber. More specifically, embodiments of this disclosure describe a biasing scheme that is configured to provide a pulsed-voltage (PV) waveform delivered from one or more pulsed-voltage (PV) generators to the one or more electrodes within the processing chamber. The plasma process(es) disclosed herein can be used to control the shape of an ion energy distribution function (IEDF) and the interaction of the plasma with a surface of a substrate during plasma processing.

公开(公告)号：US10923321B2

公开(公告)日：2021-02-16

申请号：US16790086

申请日：2020-02-13

Applicant: Applied Materials, Inc.

Inventor： Leonid Dorf ,  Evgeny Kamenetskiy ,  James Rogers ,  Olivier Luere ,  Rajinder Dhindsa ,  Viacheslav Plotnikov

IPC: H01J37/32 ,  H01L21/311 ,  H05H1/24 ,  H01L21/683

Abstract: Embodiments of this disclosure describe a feedback loop that can be used to maintain a nearly constant sheath voltage and thus creating a mono-energetic IEDF at the surface of the substrate. The system described herein consequently enables a precise control over the shape of IEDF and the profile of the features formed in the surface of the substrate.

公开(公告)号：USD797691S1

公开(公告)日：2017-09-19

申请号：US29561163

申请日：2016-04-14

Applicant: Applied Materials, Inc.

Designer： Olivier Joubert ,  Jason A. Kenney ,  Sunil Srinivasan ,  James Rogers ,  Rajinder Dhindsa ,  Vedapuram S. Achutharaman ,  Olivier Luere

公开(公告)号：US09520302B2

公开(公告)日：2016-12-13

申请号：US14934547

申请日：2015-11-06

Applicant: APPLIED MATERIALS, INC.

Inventor： Jungmin Ko ,  Sean Kang ,  Kwang-Soo Kim ,  Olivier Luere

IPC: H01L21/311

CPC classification number: H01L21/31116

Abstract: A method of processing a substrate includes depositing an oxide material on a substrate having a first region, a second region and a plurality of features, wherein the first region has a high feature density and the second region has a low feature density; and controlling a ratio of an etch rate of the oxide material in the first region to an etch rate of the oxide material in the second region by forming an ammonium hexafluorosilicate ((NH4)2SiF6) layer having a first thickness atop the oxide material in the first region and having a second thickness atop the oxide material in the second region.

Abstract translation: 一种处理衬底的方法包括在具有第一区域，第二区域和多个特征的衬底上沉积氧化物材料，其中第一区域具有高特征密度，第二区域具有低特征密度; 以及通过在所述第二区域中形成具有在所述氧化物材料的顶部的第一厚度的六氟硅酸铵（（NH 4）2 SiF 6））来控制所述第一区域中的氧化物材料的蚀刻速率与所述氧化物材料的蚀刻速率的比率 并且在第二区域中具有位于氧化物材料上方的第二厚度。

公开(公告)号：US11699572B2

公开(公告)日：2023-07-11

申请号：US16748847

申请日：2020-01-22

Applicant: Applied Materials, Inc.

Inventor： Leonid Dorf ,  Evgeny Kamenetskiy ,  James Rogers ,  Olivier Luere ,  Rajinder Dhindsa ,  Viacheslav Plotnikov

IPC: H01J37/32 ,  H01L21/311 ,  H01L21/683

CPC classification number: H01J37/32128 ,  H01J37/32082 ,  H01J37/3299 ,  H01J37/32146 ,  H01J37/32165 ,  H01J37/32174 ,  H01L21/31116 ,  H01J2237/3341 ,  H01L21/6831

Abstract: Embodiments of this disclosure describe a feedback loop that can be used to maintain a nearly constant sheath voltage and thus creating a mono-energetic IEDF at the surface of the substrate. The system described herein consequently enables a precise control over the shape of IEDF and the profile of the features formed in the surface of the substrate.

公开(公告)号：US11521849B2

公开(公告)日：2022-12-06

申请号：US16391219

申请日：2019-04-22

Applicant: Applied Materials, Inc.

Inventor： Sang Wook Park ,  Sunil Srinivasan ,  Rajinder Dhindsa ,  Jonathan Sungehul Kim ,  Lin Yu ,  Zhonghua Yao ,  Olivier Luere

IPC: H01L21/02 ,  H01L21/033 ,  C23C16/455 ,  C23C16/40 ,  C23C16/34

Abstract: Embodiments of the present disclosure provide methods and apparatus for forming a desired material layer on a substrate between, during, prior to or after a patterning process. In one embodiment, a method for forming a material layer on a substrate includes pulsing a first gas precursor onto a surface of a substrate, attaching a first element from the first gas precursor onto the surface of the substrate, maintaining a substrate temperature less than about 110 degrees Celsius, pulsing a second gas precursor onto the surface of the substrate, and attaching a second element from the second gas precursor to the first element on the surface of the substrate.

公开(公告)号：US11049760B2

公开(公告)日：2021-06-29

申请号：US15436936

申请日：2017-02-20

Applicant: Applied Materials, Inc.

Inventor： Olivier Joubert ,  Jason A. Kenney ,  Sunil Srinivasan ,  James Rogers ,  Rajinder Dhindsa ,  Vedapuram S. Achutharaman ,  Olivier Luere

IPC: H01L21/687 ,  H01J37/32 ,  H01L21/683

Abstract: The implementations described herein generally relate to a process kit suitable for use in a semiconductor process chamber, which reduces edge effects and widens the processing window with a single edge ring as compared to conventional process kits. The process kit generally includes an edge ring disposed adjacent to and surrounding a perimeter of a semiconductor substrate in a plasma chamber. A dimension of a gap between the substrate and the edge ring is less than about 1000 μm, and a height difference between the substrate and the edge ring is less than about (+/−) 300 μm. The resistivity of the ring is less than about 50 Ohm-cm.