PVD ALN film with oxygen doping for a low etch rate hardmask film
    1.
    发明授权
    PVD ALN film with oxygen doping for a low etch rate hardmask film 有权
    具有氧掺杂的PVD ALN膜用于低蚀刻速率的硬掩模膜

    公开(公告)号:US09162930B2

    公开(公告)日:2015-10-20

    申请号:US13867606

    申请日:2013-04-22

    Abstract: The present invention generally relates to a doped aluminum nitride hardmask and a method of making a doped aluminum nitride hardmask. By adding a small amount of dopant, such as oxygen, when forming the aluminum nitride hardmask, the wet etch rate of the hardmask can be significantly reduced. Additionally, due to the presence of the dopant, the grain size of the hardmask is reduced compared to a non-doped aluminum nitride hardmask. The reduced grain size leads to smoother features in the hardmask which leads to more precise etching of the underlying layer when utilizing the hardmask.

    Abstract translation: 本发明一般涉及掺杂氮化铝硬掩模和制造掺杂氮化铝硬掩模的方法。 通过在形成氮化铝硬掩模时添加少量的掺杂剂,例如氧,可以显着降低硬掩模的湿蚀刻速率。 另外,由于掺杂剂的存在,与未掺杂的氮化铝硬掩模相比,硬掩模的晶粒尺寸减小。 减小的晶粒尺寸导致在硬掩模中更平滑的特征,这导致在利用硬掩模时对底层进行更精确的蚀刻。

    Lowering tungsten resistivity by replacing titanium nitride with titanium silicon nitride
    4.
    发明授权
    Lowering tungsten resistivity by replacing titanium nitride with titanium silicon nitride 有权
    通过用氮化钛替代氮化钛来降低钨电阻率

    公开(公告)号:US09583349B2

    公开(公告)日:2017-02-28

    申请号:US14553842

    申请日:2014-11-25

    Abstract: Semiconductor devices, methods and apparatus for forming the same are provided. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions. The gate electrode stack includes a conductive film layer on a gate dielectric layer, a refractory metal silicon nitride film layer on the conductive film layer, and a tungsten film layer on the refractory metal silicon nitride film layer. In one embodiment, the method includes positioning a substrate within a processing chamber, wherein the substrate includes a source and drain region, a gate dielectric layer between the source and drain regions, and a conductive film layer on the gate dielectric layer. The method also includes depositing a refractory metal silicon nitride film layer on the conductive film layer and depositing a tungsten film layer on the refractory metal silicon nitride film layer.

    Abstract translation: 提供了用于形成半导体器件的方法和装置。 半导体器件包括在源极和漏极区域之间的衬底上具有源极和漏极区域以及栅电极堆叠的衬底。 栅极电极堆叠包括在栅极电介质层上的导电膜层,导电膜层上的难熔金属氮化硅膜层和难熔金属氮化硅膜层上的钨膜层。 在一个实施例中,该方法包括将衬底定位在处理室内,其中衬底包括源极和漏极区域,源极和漏极区域之间的栅极介电层以及栅极电介质层上的导电膜层。 该方法还包括在导电膜层上沉积难熔金属氮化硅膜层,并在难熔金属氮化硅膜层上沉积钨膜层。

    Tungsten silicide nitride films and methods of formation
    7.
    发明授权
    Tungsten silicide nitride films and methods of formation 有权
    钨硅化钨薄膜及其形成方法

    公开(公告)号:US09461137B1

    公开(公告)日:2016-10-04

    申请号:US14938559

    申请日:2015-11-11

    Abstract: Embodiments of the present disclosure include tungsten silicide nitride films and methods for depositing tungsten silicide nitride films. In some embodiments, a thin film microelectronic device includes a semiconductor substrate having a tungsten gate electrode stack comprising a tungsten silicide nitride film having a formula WxSiyNz, wherein x is about 19 to about 22 atomic percent, y is about 57 to about 61 atomic percent, and z is about 15 to about 20 atomic percent. In some embodiments, a method of processing a substrate disposed in physical vapor deposition (PVD) chamber, includes: exposing a substrate having a gate insulating layer to a plasma formed from a first process gas comprising nitrogen and argon; sputtering silicon and tungsten material from a target disposed within a processing volume of the PVD chamber; depositing atop the gate insulating layer a tungsten silicide nitride layer as described above; and depositing a bulk tungsten layer atop the tungsten silicide nitride layer.

    Abstract translation: 本公开的实施例包括硅化钨氮化物膜和用于沉积硅化钨氮化物膜的方法。 在一些实施例中,薄膜微电子器件包括具有钨栅极电极堆叠的半导体衬底,所述钨栅电极堆叠包括具有式W x Si y N z的硅化钨化硅膜,其中x为约19至约22原子%,y为约57至约61原子% ,z为约15〜约20原子%。 在一些实施例中,处理设置在物理气相沉积(PVD)室中的衬底的方法包括:将具有栅极绝缘层的衬底暴露于由包括氮和氩的第一工艺气体形成的等离子体; 从设置在PVD室的处理容积内的靶溅射硅和钨材料; 在栅极绝缘层的顶上沉积如上所述的硅化钨化硅层; 以及在硅化钨化硅层顶上沉积体钨层。

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