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    Method of manufacturing structure for connecting interconnect lines including metal layer with thickness larger than thickness of metallic compound layer
    3.
    发明授权
    Method of manufacturing structure for connecting interconnect lines including metal layer with thickness larger than thickness of metallic compound layer 有权
    制造包括厚度大于金属化合物层厚度的金属层的互连线的结构的制造方法

    公开(公告)号：US06780769B2

    公开(公告)日：2004-08-24

    申请号：US10464502

    申请日：2003-06-19

    申请人： Masahiko Fujisawa ,  Akihiko Ohsaki ,  Noboru Morimoto

    发明人： Masahiko Fujisawa ,  Akihiko Ohsaki ,  Noboru Morimoto

    IPC分类号： H01L2144

    CPC分类号： H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal layer (7), a metallic compound layer (8) and a metal layer (9) are stacked in this order when viewed from the side of a first copper interconnect line (2) and an interlayer insulating film (5) to constitute a second conductive barrier layer (20). As the material for the metal layers (7) and (9), an element having an atomic weight higher than that of copper such as tungsten (W) or tantalum (Ta) is applicable. A second copper interconnect line (6) is conductively connected to the first copper interconnect line (2) at a contact hole (12) through the second conductive barrier layer (20). As the ratio of the volume of the second copper interconnect line (6) at the region for filling a trench (11) to the volume of the second copper interconnect line (6) at the region for filling the contact hole (12) increases, tensile stress to be concentrated at the contact hole (12) becomes greater. As a result, a void is likely to be generated in the contact hole (12). In view of this, in order to improve the adhesion especially between the second copper interconnect line (6) at the region for filling the contact hole (12) and the second conductive barrier layer (20), the metal layer (9) is provided.

    摘要翻译： 从第一铜互连线（2）和层间绝缘膜（5）的侧面观察时，依次层叠金属层（7），金属化合物层（8）和金属层（9），构成 第二导电阻挡层（20）。 作为金属层（7）和（9）的材料，可以使用原子量高于诸如钨（W）或钽（Ta）的铜的元素。 第二铜互连线（6）通过第二导电阻挡层（20）在接触孔（12）处导电地连接到第一铜互连线（2）。 由于在填充接触孔（12）的区域处，用于填充沟槽（11）的区域处的第二铜互连线（6）的体积与第二铜互连线（6）的体积的比率增加， 要集中在接触孔（12）处的拉伸应力变大。 结果，在接触孔（12）中容易产生空隙。 鉴于此，为了改善在用于填充接触孔（12）的区域和第二导电阻挡层（20）之间的第二铜互连线（6）之间的粘合性，提供了金属层（9） 。

    Structure for connecting interconnect lines with interposed layer including metal layers and metallic compound layer
    4.
    发明授权
    Structure for connecting interconnect lines with interposed layer including metal layers and metallic compound layer 有权
    用于连接具有包括金属层和金属化合物层的插入层的互连线的结构

    公开(公告)号：US06624516B2

    公开(公告)日：2003-09-23

    申请号：US09978005

    申请日：2001-10-17

    申请人： Masahiko Fujisawa ,  Akihiko Ohsaki ,  Noboru Morimoto

    发明人： Masahiko Fujisawa ,  Akihiko Ohsaki ,  Noboru Morimoto

    IPC分类号： H01L2348

    CPC分类号： H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal layer (7), a metallic compound layer (8) and a metal layer (9) are stacked in this order when viewed from the side of a first copper interconnect line (2) and an interlayer insulating film (5) to constitute a second conductive barrier layer (20). As the material for the metal layers (7) and (9), an element having an atomic weight higher than that of copper such as tungsten (W) or tantalum (Ta) is applicable. A second copper interconnect line (6) is conductively connected to the first copper interconnect line (2) at a contact hole (12) through the second conductive barrier layer (20). As the ratio of the volume of the second copper interconnect line (6) at the region for filling a trench (11) to the volume of the second copper interconnect line (6) at the region for filling the contact hole (12) increases, tensile stress to be concentrated at the contact hole (12) becomes greater. As a result, a void is likely to be generated in the contact hole (12). In view of this, in order to improve the adhesion especially between the second copper interconnect line (6) at the region for filling the contact hole (12) and the second conductive barrier layer (20), the metal layer (9) is provided.

    摘要翻译： 从第一铜互连线（2）和层间绝缘膜（5）的侧面观察时，依次层叠金属层（7），金属化合物层（8）和金属层（9），构成 第二导电阻挡层（20）。 作为金属层（7）和（9）的材料，可以使用原子量高于诸如钨（W）或钽（Ta）的铜的元素。 第二铜互连线（6）通过第二导电阻挡层（20）在接触孔（12）处导电地连接到第一铜互连线（2）。 由于在填充接触孔（12）的区域处，用于填充沟槽（11）的区域处的第二铜互连线（6）的体积与第二铜互连线（6）的体积的比率增加， 要集中在接触孔（12）处的拉伸应力变大。 结果，在接触孔（12）中容易产生空隙。 鉴于此，为了改善在用于填充接触孔（12）的区域和第二导电阻挡层（20）之间的第二铜互连线（6）之间的粘合性，提供了金属层（9） 。

    Wiring structure for an integrated circuit
    6.
    发明授权
    Wiring structure for an integrated circuit 失效
    集成电路的接线结构

    公开(公告)号：US06664641B2

    公开(公告)日：2003-12-16

    申请号：US10261653

    申请日：2002-10-02

    申请人： Akihiko Ohsaki ,  Masahiko Fujisawa ,  Noboru Morimoto

    发明人： Akihiko Ohsaki ,  Masahiko Fujisawa ,  Noboru Morimoto

    IPC分类号： H01L2710

    CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A wire width and a wiring space of each of signal wires 1 and ground/power wires 2 are determined to be a wire width W1 (the minimum wire width) and a wiring space S1, respectively. A wire width and a wiring space of the via-hole neighboring region 1a or 2a are determined to be a wire width W2 (>W1) and a wiring space S2 (

    摘要翻译： 信号线1和接地/电力线2的线宽和布线空间分别被确定为线宽W1（最小线宽）和布线空间S1。 通孔相邻区域1a或2a的线宽度和布线空间分别被确定为线宽W2（> W1）和布线空间S2（ = 0.6}。 此外，信号线1和接地/电力线2具有与宽度比（T1 / W1）等于或高于2的线材厚度T1相同的线材厚度。

    Semiconductor device and method for reducing contact resistance between an electrode and a semiconductor substrate
    10.
    发明授权
    Semiconductor device and method for reducing contact resistance between an electrode and a semiconductor substrate 失效
    用于降低电极和半导体衬底之间的接触电阻的半导体器件和方法

    公开(公告)号：US06716731B2

    公开(公告)日：2004-04-06

    申请号：US09838227

    申请日：2001-04-20

    申请人： Masahiko Fujisawa

    发明人： Masahiko Fujisawa

    IPC分类号： H01L213205

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A main electrode is connected to an n-type semiconductor layer selectively formed on a major surface of a silicon substrate. A silicide layer is interposed between the main electrode and the semiconductor layer. The silicide layer is heat-treated at 600° C. to 850° C. for at least 30 minutes, to have an epitaxial layer selectively epitaxially growing in a specific direction such as the direction toward the semiconductor layer. Therefore, irregularities are formed on the interface between the suicide layer and the semiconductor layer. The interface resistivity between the silicide layer and the semiconductor layer is low due to the presence of the epitaxial layer, and besides the contact area of the interface is large due to the irregularities of the interface. Consequently, the contact resistance between the main electrode and the semiconductor layer is effectively reduced. Thus, the contact resistance between the main electrode and the semiconductor substrate is reduced.

    摘要翻译： 主电极连接到选择性地形成在硅衬底的主表面上的n型半导体层。 硅化物层介于主电极和半导体层之间。 将硅化物层在600℃至850℃下热处理至少30分钟，以使外延层选择性地沿着朝向半导体层的<110>方向的特定方向外延生长。 因此，在硅化物层和半导体层之间的界面上形成凹凸。 由于外延层的存在，硅化物层和半导体层之间的界面电阻率低，并且由于界面的不规则性，接口的接触面积也很大。 因此，主电极和半导体层之间的接触电阻被有效地降低。 因此，主电极和半导体衬底之间的接触电阻降低。