公开(公告)号：US06791194B1

公开(公告)日：2004-09-14

申请号：US09493210

申请日：2000-01-28

申请人： Akira Nagai ,  Shuji Eguchi ,  Masahiko Ogino ,  Masanori Segawa ,  Toshiak Ishii ,  Nobutake Tsuyuno ,  Hiroyoshi Kokaku ,  Rie Hattori ,  Makoto Morishima ,  Ichiro Anjoh ,  Kunihiro Tsubosaki ,  Chuichi Miyazaki ,  Makoto Kitano ,  Mamoru Mita ,  Norio Okabe

发明人： Akira Nagai ,  Shuji Eguchi ,  Masahiko Ogino ,  Masanori Segawa ,  Toshiak Ishii ,  Nobutake Tsuyuno ,  Hiroyoshi Kokaku ,  Rie Hattori ,  Makoto Morishima ,  Ichiro Anjoh ,  Kunihiro Tsubosaki ,  Chuichi Miyazaki ,  Makoto Kitano ,  Mamoru Mita ,  Norio Okabe

IPC分类号： H01L2348

CPC分类号： H01L24/50 ,  H01L23/3107 ,  H01L23/4951 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/10329 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250° C.).

摘要翻译： 通过在半导体封装结构中设置用于吸收安装基板和半导体元件之间的热膨胀差的缓冲体，即使使用有机材料来安装基板，也可获得具有优异的连接可靠性的半导体器件。 使用薄膜材料作为用于缓冲由安装基板和半导体元件之间的热膨胀差异产生的热应力的本体。 膜材料在回流温度范围（200-250℃）中的弹性模量至少为1MPa。

公开(公告)号：US07202570B2

公开(公告)日：2007-04-10

申请号：US10724092

申请日：2003-12-01

申请人： Akira Nagai ,  Shuji Eguchi ,  Masahiko Ogino ,  Masanori Segawa ,  Toshiak Ishii ,  Nobutake Tsuyuno ,  Hiroyoshi Kokaku ,  Rie Hattori ,  Makoto Morishima ,  Ichiro Anjoh ,  Kunihiro Tsubosaki ,  Chuichi Miyazaki ,  Makoto Kitano ,  Mamoru Mita ,  Norio Okabe

发明人： Akira Nagai ,  Shuji Eguchi ,  Masahiko Ogino ,  Masanori Segawa ,  Toshiak Ishii ,  Nobutake Tsuyuno ,  Hiroyoshi Kokaku ,  Rie Hattori ,  Makoto Morishima ,  Ichiro Anjoh ,  Kunihiro Tsubosaki ,  Chuichi Miyazaki ,  Makoto Kitano ,  Mamoru Mita ,  Norio Okabe

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44 ,  H01L21/48 ,  B32B3/06 ,  B32B7/12

CPC分类号： H01L24/06 ,  H01L23/3107 ,  H01L23/4951 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06136 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30107 ,  H01L2924/351 ,  Y10T156/107 ,  Y10T428/249955 ,  Y10T428/28 ,  Y10T428/2848 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200–250° C.).

摘要翻译： 具有优异的连接可靠性的半导体器件通过在半导体封装结构中设置用于吸收安装基板和半导体元件之间的热膨胀差的缓冲体，即使将有机材料用于安装基板也是可以获得的。 使用薄膜材料作为用于缓冲由安装基板和半导体元件之间的热膨胀差异产生的热应力的本体。 膜材料在回流温度范围（200-250℃）中的弹性模量至少为1MPa。

公开(公告)号：US6114753A

公开(公告)日：2000-09-05

申请号：US857674

申请日：1997-05-16

申请人： Akira Nagai ,  Shuji Eguchi ,  Masahiko Ogino ,  Masanori Segawa ,  Toshiak Ishii ,  Nobutake Tsuyuno ,  Hiroyoshi Kokaku ,  Rie Hattori ,  Makoto Morishima ,  Ichiro Anjoh ,  Kunihiro Tsubosaki ,  Chuichi Miyazaki ,  Makoto Kitano ,  Mamoru Mita ,  Norio Okabe

发明人： Akira Nagai ,  Shuji Eguchi ,  Masahiko Ogino ,  Masanori Segawa ,  Toshiak Ishii ,  Nobutake Tsuyuno ,  Hiroyoshi Kokaku ,  Rie Hattori ,  Makoto Morishima ,  Ichiro Anjoh ,  Kunihiro Tsubosaki ,  Chuichi Miyazaki ,  Makoto Kitano ,  Mamoru Mita ,  Norio Okabe

IPC分类号： H01L21/60 ,  H01L23/12 ,  H01L23/31 ,  H01L23/495 ,  H01L23/485

CPC分类号： H01L24/06 ,  H01L23/3107 ,  H01L23/4951 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  Y10T428/28 ,  Y10T428/2848

摘要： A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250.degree. C.).

摘要翻译： 具有优异的连接可靠性的半导体器件通过在半导体封装结构中设置用于吸收安装基板和半导体元件之间的热膨胀差的缓冲体，即使将有机材料用于安装基板也是可以获得的。 使用薄膜材料作为用于缓冲由安装基板和半导体元件之间的热膨胀差异产生的热应力的本体。 膜材料的回流温度范围（200-250℃）的弹性模量至少为1MPa。

公开(公告)号：US06433440B1

公开(公告)日：2002-08-13

申请号：US09092138

申请日：1998-06-05

申请人： Masahiko Ogino ,  Shuji Eguchi ,  Akira Nagai ,  Takumi Ueno ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Toshiaki Ishii ,  Ichiro Anjoh ,  Asao Nishimura ,  Chuichi Miyazaki ,  Mamoru Mita ,  Norio Okabe

发明人： Masahiko Ogino ,  Shuji Eguchi ,  Akira Nagai ,  Takumi Ueno ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Toshiaki Ishii ,  Ichiro Anjoh ,  Asao Nishimura ,  Chuichi Miyazaki ,  Mamoru Mita ,  Norio Okabe

IPC分类号： H01L2348

CPC分类号： H01L24/50 ,  H01L23/3107 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/32 ,  H01L2224/29111 ,  H01L2224/73215 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/29099 ,  H01L2924/00

摘要： In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.

摘要翻译： 在具有三层缓冲层的半导体器件中，作为在半导体芯片5和布线4之间的应力缓冲层，芯层1具有三维网状结构的互连泡沫的芯层1和设置在芯层两侧的粘合层2 为了降低半导体器件与封装衬底之间产生的热应力，其中芯层1与总缓冲层的厚度比至少为0.2，可以通过使用这种缓冲层来简化制造工艺，从而提高批量生产 容量和提高包装可靠性。

公开(公告)号：US07038325B2

公开(公告)日：2006-05-02

申请号：US10830051

申请日：2004-04-23

申请人： Masahiko Ogino ,  Shuji Eguchi ,  Akira Nagai ,  Takumi Ueno ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Toshiaki Ishii ,  Ichiro Anjoh ,  Asao Nishimura ,  Chuichi Miyazaki ,  Mamoru Mita ,  Norio Okabe

发明人： Masahiko Ogino ,  Shuji Eguchi ,  Akira Nagai ,  Takumi Ueno ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Toshiaki Ishii ,  Ichiro Anjoh ,  Asao Nishimura ,  Chuichi Miyazaki ,  Mamoru Mita ,  Norio Okabe

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/50 ,  H01L23/3107 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/32 ,  H01L2224/29111 ,  H01L2224/73215 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/29099 ,  H01L2924/00

摘要： In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of the core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.

摘要翻译： 在具有三层缓冲层的半导体器件中，作为在半导体芯片5和布线4之间的应力缓冲层，芯层1具有三维网状结构的互连泡沫的芯层1和设置在芯层两侧的粘合层2 为了减小半导体器件与封装衬底之间产生的热应力，其中芯层1与总缓冲层的厚度比至少为0.2，可以通过使用这种缓冲层来简化制造工艺，从而提高质量 生产能力和提高包装可靠性。

公开(公告)号：US07091620B2

公开(公告)日：2006-08-15

申请号：US11116209

申请日：2005-04-28

申请人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masnori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Hiroshi Koyama ,  Akira Nagai ,  Masahiko Ogino

发明人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masnori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Hiroshi Koyama ,  Akira Nagai ,  Masahiko Ogino

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/50 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/50 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

摘要： A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

公开(公告)号：US20050200019A1

公开(公告)日：2005-09-15

申请号：US11116209

申请日：2005-04-28

申请人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masnori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Hiroshi Koyama ,  Akira Nagai ,  Masahiko Ogino

发明人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masnori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Hiroshi Koyama ,  Akira Nagai ,  Masahiko Ogino

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/48 ,  H01L21/44

CPC分类号： H01L24/50 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/50 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

摘要： A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

摘要翻译： 半导体器件包括形成有连接端子的半导体芯片，插入在芯片的主表面之间的弹性结构和形成有连接到连接端子的布线的布线基板，以及连接到连接端子的另一端的凸起电极 布线。 连接端子可以在芯片主表面的中心部分或周边部分，并且弹性结构和布线基板都不设置在连接端子的位置处。 树脂体至少密封连接端子和暴露的布线的第一端（引线）。 在连接端子位于芯片主表面的周边部分的方案中，布线基板突出超过布置有连接端子的芯片边界，并且树脂体形状被布线基板的突出部分限制 。

公开(公告)号：US20050212142A1

公开(公告)日：2005-09-29

申请号：US11116308

申请日：2005-04-28

申请人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masnori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Hiroshi Koyama ,  Akira Nagai ,  Masahiko Ogino

发明人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masnori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Hiroshi Koyama ,  Akira Nagai ,  Masahiko Ogino

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/48 ,  H01L21/44

CPC分类号： H01L24/50 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/86 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/50 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

摘要： A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

摘要翻译： 半导体器件包括形成有连接端子的半导体芯片，插入在芯片的主表面之间的弹性结构和形成有连接到连接端子的布线的布线基板，以及连接到连接端子的另一端的凸起电极 布线。 连接端子可以在芯片主表面的中心部分或周边部分，并且弹性结构和布线基板都不设置在连接端子的位置处。 树脂体至少密封连接端子和暴露的布线的第一端（引线）。 在连接端子位于芯片主表面的周边部分的方案中，布线基板突出超过布置有连接端子的芯片边界，并且树脂体形状被布线基板的突出部分限制 。

公开(公告)号：US06515371B2

公开(公告)日：2003-02-04

申请号：US09983177

申请日：2001-10-23

申请人： Yukiharu Akiyama ,  Tomoaki Kudaishi ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Asao Nishimura ,  Ichiro Anjo ,  Kunihiro Tsubosaki ,  Chuichi Miyazaki ,  Hiroshi Koyama ,  Masanori Shibamoto ,  Akira Nagai ,  Masahiko Ogino

发明人： Yukiharu Akiyama ,  Tomoaki Kudaishi ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Asao Nishimura ,  Ichiro Anjo ,  Kunihiro Tsubosaki ,  Chuichi Miyazaki ,  Hiroshi Koyama ,  Masanori Shibamoto ,  Akira Nagai ,  Masahiko Ogino

IPC分类号： H01L2348

CPC分类号： H01L24/50 ,  H01L23/3114 ,  H01L23/49572 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/1433 ,  H01L2924/3025

摘要： A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.

摘要翻译： 一种半导体器件，包括在其主表面的周边部分中具有连接端子的半导体芯片; 设置在主表面上的弹性体，使连接端子露出; 绝缘带，形成在弹性体上并且在连接端子所在的区域中具有开口; 多个引线形成在绝缘带的顶表面上，每个引线的一端连接到一个连接端子，另一端设置在弹性体上; 形成在多个引线的另一端上的多个凸起电极; 以及用于密封连接端子和每个引线的一端的树脂体，其中绝缘带突出超过设置有多个连接端子的芯片，并且其中树脂体的形状受到 绝缘胶带

公开(公告)号：US06639323B2

公开(公告)日：2003-10-28

申请号：US09983286

申请日：2001-10-23

申请人： Yukiharu Akiyama ,  Tomoaki Kudaishi ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Asao Nishimura ,  Ichiro Anjo ,  Kunihiro Tsubosaki ,  Chuichi Miyazaki ,  Hiroshi Koyama ,  Masanori Shibamoto ,  Akira Nagai ,  Masahiko Ogino

发明人： Yukiharu Akiyama ,  Tomoaki Kudaishi ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Asao Nishimura ,  Ichiro Anjo ,  Kunihiro Tsubosaki ,  Chuichi Miyazaki ,  Hiroshi Koyama ,  Masanori Shibamoto ,  Akira Nagai ,  Masahiko Ogino

IPC分类号： H01L2348

CPC分类号： H01L24/50 ,  H01L23/3114 ,  H01L23/49572 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/1433 ,  H01L2924/3025

摘要： A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.