公开(公告)号：US06433440B1

公开(公告)日：2002-08-13

申请号：US09092138

申请日：1998-06-05

申请人： Masahiko Ogino ,  Shuji Eguchi ,  Akira Nagai ,  Takumi Ueno ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Toshiaki Ishii ,  Ichiro Anjoh ,  Asao Nishimura ,  Chuichi Miyazaki ,  Mamoru Mita ,  Norio Okabe

发明人： Masahiko Ogino ,  Shuji Eguchi ,  Akira Nagai ,  Takumi Ueno ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Toshiaki Ishii ,  Ichiro Anjoh ,  Asao Nishimura ,  Chuichi Miyazaki ,  Mamoru Mita ,  Norio Okabe

IPC分类号： H01L2348

CPC分类号： H01L24/50 ,  H01L23/3107 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/32 ,  H01L2224/29111 ,  H01L2224/73215 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/29099 ,  H01L2924/00

摘要： In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.

摘要翻译： 在具有三层缓冲层的半导体器件中，作为在半导体芯片5和布线4之间的应力缓冲层，芯层1具有三维网状结构的互连泡沫的芯层1和设置在芯层两侧的粘合层2 为了降低半导体器件与封装衬底之间产生的热应力，其中芯层1与总缓冲层的厚度比至少为0.2，可以通过使用这种缓冲层来简化制造工艺，从而提高批量生产 容量和提高包装可靠性。

公开(公告)号：US07038325B2

公开(公告)日：2006-05-02

申请号：US10830051

申请日：2004-04-23

申请人： Masahiko Ogino ,  Shuji Eguchi ,  Akira Nagai ,  Takumi Ueno ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Toshiaki Ishii ,  Ichiro Anjoh ,  Asao Nishimura ,  Chuichi Miyazaki ,  Mamoru Mita ,  Norio Okabe

发明人： Masahiko Ogino ,  Shuji Eguchi ,  Akira Nagai ,  Takumi Ueno ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Toshiaki Ishii ,  Ichiro Anjoh ,  Asao Nishimura ,  Chuichi Miyazaki ,  Mamoru Mita ,  Norio Okabe

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/50 ,  H01L23/3107 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/32 ,  H01L2224/29111 ,  H01L2224/73215 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/29099 ,  H01L2924/00

摘要： In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of the core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.

摘要翻译： 在具有三层缓冲层的半导体器件中，作为在半导体芯片5和布线4之间的应力缓冲层，芯层1具有三维网状结构的互连泡沫的芯层1和设置在芯层两侧的粘合层2 为了减小半导体器件与封装衬底之间产生的热应力，其中芯层1与总缓冲层的厚度比至少为0.2，可以通过使用这种缓冲层来简化制造工艺，从而提高质量 生产能力和提高包装可靠性。

公开(公告)号：US06791194B1

公开(公告)日：2004-09-14

申请号：US09493210

申请日：2000-01-28

申请人： Akira Nagai ,  Shuji Eguchi ,  Masahiko Ogino ,  Masanori Segawa ,  Toshiak Ishii ,  Nobutake Tsuyuno ,  Hiroyoshi Kokaku ,  Rie Hattori ,  Makoto Morishima ,  Ichiro Anjoh ,  Kunihiro Tsubosaki ,  Chuichi Miyazaki ,  Makoto Kitano ,  Mamoru Mita ,  Norio Okabe

发明人： Akira Nagai ,  Shuji Eguchi ,  Masahiko Ogino ,  Masanori Segawa ,  Toshiak Ishii ,  Nobutake Tsuyuno ,  Hiroyoshi Kokaku ,  Rie Hattori ,  Makoto Morishima ,  Ichiro Anjoh ,  Kunihiro Tsubosaki ,  Chuichi Miyazaki ,  Makoto Kitano ,  Mamoru Mita ,  Norio Okabe

IPC分类号： H01L2348

CPC分类号： H01L24/50 ,  H01L23/3107 ,  H01L23/4951 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/10329 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250° C.).

摘要翻译： 通过在半导体封装结构中设置用于吸收安装基板和半导体元件之间的热膨胀差的缓冲体，即使使用有机材料来安装基板，也可获得具有优异的连接可靠性的半导体器件。 使用薄膜材料作为用于缓冲由安装基板和半导体元件之间的热膨胀差异产生的热应力的本体。 膜材料在回流温度范围（200-250℃）中的弹性模量至少为1MPa。

公开(公告)号：US07202570B2

公开(公告)日：2007-04-10

申请号：US10724092

申请日：2003-12-01

申请人： Akira Nagai ,  Shuji Eguchi ,  Masahiko Ogino ,  Masanori Segawa ,  Toshiak Ishii ,  Nobutake Tsuyuno ,  Hiroyoshi Kokaku ,  Rie Hattori ,  Makoto Morishima ,  Ichiro Anjoh ,  Kunihiro Tsubosaki ,  Chuichi Miyazaki ,  Makoto Kitano ,  Mamoru Mita ,  Norio Okabe

发明人： Akira Nagai ,  Shuji Eguchi ,  Masahiko Ogino ,  Masanori Segawa ,  Toshiak Ishii ,  Nobutake Tsuyuno ,  Hiroyoshi Kokaku ,  Rie Hattori ,  Makoto Morishima ,  Ichiro Anjoh ,  Kunihiro Tsubosaki ,  Chuichi Miyazaki ,  Makoto Kitano ,  Mamoru Mita ,  Norio Okabe

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44 ,  H01L21/48 ,  B32B3/06 ,  B32B7/12

CPC分类号： H01L24/06 ,  H01L23/3107 ,  H01L23/4951 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06136 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30107 ,  H01L2924/351 ,  Y10T156/107 ,  Y10T428/249955 ,  Y10T428/28 ,  Y10T428/2848 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200–250° C.).

摘要翻译： 具有优异的连接可靠性的半导体器件通过在半导体封装结构中设置用于吸收安装基板和半导体元件之间的热膨胀差的缓冲体，即使将有机材料用于安装基板也是可以获得的。 使用薄膜材料作为用于缓冲由安装基板和半导体元件之间的热膨胀差异产生的热应力的本体。 膜材料在回流温度范围（200-250℃）中的弹性模量至少为1MPa。

公开(公告)号：US6114753A

公开(公告)日：2000-09-05

申请号：US857674

申请日：1997-05-16

申请人： Akira Nagai ,  Shuji Eguchi ,  Masahiko Ogino ,  Masanori Segawa ,  Toshiak Ishii ,  Nobutake Tsuyuno ,  Hiroyoshi Kokaku ,  Rie Hattori ,  Makoto Morishima ,  Ichiro Anjoh ,  Kunihiro Tsubosaki ,  Chuichi Miyazaki ,  Makoto Kitano ,  Mamoru Mita ,  Norio Okabe

发明人： Akira Nagai ,  Shuji Eguchi ,  Masahiko Ogino ,  Masanori Segawa ,  Toshiak Ishii ,  Nobutake Tsuyuno ,  Hiroyoshi Kokaku ,  Rie Hattori ,  Makoto Morishima ,  Ichiro Anjoh ,  Kunihiro Tsubosaki ,  Chuichi Miyazaki ,  Makoto Kitano ,  Mamoru Mita ,  Norio Okabe

IPC分类号： H01L21/60 ,  H01L23/12 ,  H01L23/31 ,  H01L23/495 ,  H01L23/485

CPC分类号： H01L24/06 ,  H01L23/3107 ,  H01L23/4951 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  Y10T428/28 ,  Y10T428/2848

摘要： A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250.degree. C.).

摘要翻译： 具有优异的连接可靠性的半导体器件通过在半导体封装结构中设置用于吸收安装基板和半导体元件之间的热膨胀差的缓冲体，即使将有机材料用于安装基板也是可以获得的。 使用薄膜材料作为用于缓冲由安装基板和半导体元件之间的热膨胀差异产生的热应力的本体。 膜材料的回流温度范围（200-250℃）的弹性模量至少为1MPa。

公开(公告)号：US06888230B1

公开(公告)日：2005-05-03

申请号：US09429297

申请日：1999-10-28

申请人： Masahiko Ogino ,  Takumi Ueno ,  Shuji Eguchi ,  Akira Nagai ,  Toshiya Satoh ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Tadanori Segawa ,  Nobutake Tsuyuno ,  Asao Nishimura ,  Ichiro Anjoh

发明人： Masahiko Ogino ,  Takumi Ueno ,  Shuji Eguchi ,  Akira Nagai ,  Toshiya Satoh ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Tadanori Segawa ,  Nobutake Tsuyuno ,  Asao Nishimura ,  Ichiro Anjoh

IPC分类号： H01L23/12 ,  H01L21/301 ,  H01L21/46 ,  H01L21/48 ,  H01L21/50 ,  H01L21/60 ,  H01L23/28 ,  H01L23/31 ,  H01L23/50 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3171 ,  H01L23/3114 ,  H01L23/3164 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/1147 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2924/00012

摘要： Semiconductor devices, semiconductor wafers, and semiconductor modules are provided, wherein: the semiconductor device has a small warp; damage at the chip edge and cracks occurring in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor includes a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on the same plane.

摘要翻译： 提供半导体器件，半导体晶片和半导体模块，其中：半导体器件具有小的翘曲; 几乎不产生芯片边缘的损伤和在滴下试验中发生的裂纹; 半导体装置的安装可靠性和大规模生产性优异。 该半导体包括半导体芯片64; 设置在半导体芯片的形成有电路和电极的平面上的多孔应力缓和层3; 设置在应力缓和层上并与电极连接的电路层2; 和设置在电路层上的外部端子10; 其中在半导体芯片的与应力缓和层相反的平面上形成有机保护膜7，并且应力缓和层，半导体芯片6和保护膜7的各个侧面在外部暴露在外部 飞机

公开(公告)号：US07217992B2

公开(公告)日：2007-05-15

申请号：US10861523

申请日：2004-06-07

申请人： Masahiko Ogino ,  Takumi Ueno ,  Shuji Eguchi ,  Akira Nagai ,  Toshiya Satoh ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Tadanori Segawa ,  Nobutake Tsuyuno ,  Asao Nishimura ,  Ichiro Anjoh

发明人： Masahiko Ogino ,  Takumi Ueno ,  Shuji Eguchi ,  Akira Nagai ,  Toshiya Satoh ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Tadanori Segawa ,  Nobutake Tsuyuno ,  Asao Nishimura ,  Ichiro Anjoh

IPC分类号： H01L23/02 ,  H01L23/28 ,  H01L21/00

CPC分类号： H01L23/3171 ,  H01L23/3114 ,  H01L23/3164 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/1147 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2924/00012

摘要： Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility.The semiconductor device 17 comprising: a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on a same plane.

摘要翻译： 提供半导体器件，半导体晶片和半导体模块：其中半导体器件具有小的翘曲; 几乎不产生芯片边缘的损坏和跌落试验中的裂纹; 半导体装置的安装可靠性和大规模生产性优异。 半导体器件17包括：半导体芯片64; 设置在半导体芯片的形成有电路和电极的平面上的多孔应力缓和层3; 设置在应力缓和层上并与电极连接的电路层2; 和设置在电路层上的外部端子10; 其中在半导体芯片的与应力缓和层相反的平面上形成有机保护膜7，并且应力缓和层，半导体芯片6和保护膜7的各个侧面在外部暴露在外部 飞机

公开(公告)号：US6114005A

公开(公告)日：2000-09-05

申请号：US859659

申请日：1997-05-20

申请人： Akira Nagai ,  Masatsugu Ogata ,  Shuji Eguchi ,  Masahiko Ogino ,  Toshiaki Ishii ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Ryo Moteki ,  Ichiro Anjoh

发明人： Akira Nagai ,  Masatsugu Ogata ,  Shuji Eguchi ,  Masahiko Ogino ,  Toshiaki Ishii ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Ryo Moteki ,  Ichiro Anjoh

IPC分类号： B32B27/12 ,  H01L23/14 ,  H05K1/03 ,  B32B5/12

CPC分类号： B32B27/12 ,  H01L23/145 ,  H05K1/0373 ,  H01L2224/48227 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K2201/015 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/029 ,  H05K2201/068 ,  Y10S428/901 ,  Y10T428/24132 ,  Y10T428/254

摘要： A laminate capable of mounting semiconductor elements thereon; comprising an insulating layer which is constituted by a resin portion of sea-island structure and a woven reinforcement. The resin portion of sea-island structure is, for example, such that a resin as islands are dispersed in a resin as a matrix. Thus, the insulating layer exhibits a coefficient of thermal expansion of 3.0.about.10 (ppm/K) in a planar direction thereof and a glass transition temperature of 150.about.300 (.degree.C.). Owing to these physical properties, thermal stresses which the laminate undergoes in packaging the semiconductor elements thereon can be reduced, so that the connections of the laminate with the semiconductor elements can be made highly reliable.

摘要翻译： 能够在其上安装半导体元件的层压体; 包括由海岛结构的树脂部分和织造加强件构成的绝缘层。 例如，海岛结构的树脂部分使得岛状树脂以树脂为基体分散。 因此，绝缘层在其平面方向上的热膨胀系数为3.0D（ppm / K），玻璃化转变温度为150℃（℃）。 由于这些物理性质，可以减少层压体在其上封装半导体元件时的热应力，使得层压体与半导体元件的连接可以高度可靠。

公开(公告)号：US5677045A

公开(公告)日：1997-10-14

申请号：US430553

申请日：1995-04-28

申请人： Akira Nagai ,  Masatsugu Ogata ,  Shuji Eguchi ,  Masahiko Ogino ,  Toshiaki Ishii ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Ryo Moteki ,  Ichiro Anjoh

发明人： Akira Nagai ,  Masatsugu Ogata ,  Shuji Eguchi ,  Masahiko Ogino ,  Toshiaki Ishii ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Ryo Moteki ,  Ichiro Anjoh

IPC分类号： B32B27/12 ,  H01L23/14 ,  H05K1/03 ,  B32B7/00 ,  B32B3/02 ,  B32B5/12 ,  B32B5/16

CPC分类号： B32B27/12 ,  H01L23/145 ,  H05K1/0373 ,  H01L2224/48227 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K2201/015 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/029 ,  H05K2201/068 ,  Y10S428/901 ,  Y10T428/23986 ,  Y10T428/24132 ,  Y10T428/254 ,  Y10T442/20 ,  Y10T442/209 ,  Y10T442/2123 ,  Y10T442/3854 ,  Y10T442/3919

摘要： A laminate capable of mounting semiconductor elements thereon; comprising an insulating layer which is constituted by a resin portion of sea-island structure and a woven reinforcement. The resin portion of sea-island structure is, for example, such that a resin as islands are dispersed in a resin as a matrix. Thus, the insulating layer exhibits a coefficient of thermal expansion of 3.0.about.10 (ppm/K) in a planar direction thereof and a glass transition temperature of 150.about.300 (.degree.C.). Owing to these physical properties, thermal stresses which the laminate undergoes in packaging the semiconductor elements thereon can be reduced, so that the connections of the laminate with the semiconductor elements can be made highly reliable.

摘要翻译： 能够在其上安装半导体元件的层压体; 包括由海岛结构的树脂部分和织造加强件构成的绝缘层。 例如，海岛结构的树脂部分使得岛状树脂以树脂为基体分散。 因此，绝缘层在其平面方向上的热膨胀系数为3.0D（ppm / K），玻璃化转变温度为150℃（℃）。 由于这些物理性质，可以减少层压体在其上封装半导体元件时的热应力，使得层压体与半导体元件的连接可以高度可靠。

公开(公告)号：US20050200019A1

公开(公告)日：2005-09-15

申请号：US11116209

申请日：2005-04-28

申请人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masnori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Hiroshi Koyama ,  Akira Nagai ,  Masahiko Ogino

发明人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masnori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Hiroshi Koyama ,  Akira Nagai ,  Masahiko Ogino

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/48 ,  H01L21/44

CPC分类号： H01L24/50 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/50 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

摘要： A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

摘要翻译： 半导体器件包括形成有连接端子的半导体芯片，插入在芯片的主表面之间的弹性结构和形成有连接到连接端子的布线的布线基板，以及连接到连接端子的另一端的凸起电极 布线。 连接端子可以在芯片主表面的中心部分或周边部分，并且弹性结构和布线基板都不设置在连接端子的位置处。 树脂体至少密封连接端子和暴露的布线的第一端（引线）。 在连接端子位于芯片主表面的周边部分的方案中，布线基板突出超过布置有连接端子的芯片边界，并且树脂体形状被布线基板的突出部分限制 。