公开(公告)号：US20220298625A1

公开(公告)日：2022-09-22

申请号：US17834633

申请日：2022-06-07

申请人： Applied Materials, Inc.

发明人： Sang-Ho YU ,  Kevin MORAES ,  Seshadri GANGULI ,  Hua CHUNG ,  See-Eng PHAN

IPC分类号： C23C16/16 ,  H01L21/324 ,  H01L21/768 ,  C23C16/02 ,  C23C16/18 ,  H01L21/02 ,  H01L21/285 ,  C23C16/455 ,  C23C16/50

摘要： Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface. In another embodiment, a deposition-treatment cycle includes performing the vapor deposition process and subsequently a post-treatment process, which deposition-treatment cycle may be repeated to form multiple cobalt capping layers.

公开(公告)号：US20170098575A1

公开(公告)日：2017-04-06

申请号：US15285011

申请日：2016-10-04

申请人： APPLIED MATERIALS, INC.

发明人： Sree Rangasai V. KESAPRAGADA ,  Kevin MORAES ,  Srinivas GUGGILLA ,  He REN ,  Mehul NAIK ,  David THOMPSON ,  Weifeng YE ,  Yana CHENG ,  Yong CAO ,  Xianmin TANG ,  Paul F. MA ,  Deenesh PADHI

IPC分类号： H01L21/768 ,  H01L21/02

CPC分类号： H01L21/76832 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834

摘要： In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

公开(公告)号：US20200373134A1

公开(公告)日：2020-11-26

申请号：US16848614

申请日：2020-04-14

申请人： Applied Materials, Inc.

发明人： Alexander N. LERNER ,  Michael P. KARAZIM ,  Andrew J. CONSTANT ,  Jeffrey A. BRODINE ,  Kim Ramkumar VELLORE ,  Kevin MORAES ,  Roey SHAVIV

IPC分类号： H01J37/32 ,  C23C16/04 ,  H01L21/68 ,  H01L21/677 ,  H01L21/673

摘要： An alignment module for housing and cleaning masks. The alignment module comprises a mask stocker, a cleaning chamber, an alignment chamber, an alignment stage a transfer robot. The mask stocker is configured to house a mask cassette configured to store a plurality of masks. The cleaning chamber is configured to clean the plurality of masks by providing one or more cleaning gases into a chamber after a mask is inserted into the cleaning chamber. The alignment stage is configured to support a carrier and a substrate. The transfer robot is configured to transfer a mask from one or more of the alignment stage and the mask stocker to the cleaning chamber.

公开(公告)号：US20150214475A1

公开(公告)日：2015-07-30

申请号：US14677761

申请日：2015-04-02

申请人： Applied Materials, Inc.

发明人： Roman GOUK ,  Steven VERHAVERBEKE ,  Alexander KONTOS ,  Adolph Miller ALLEN ,  Kevin MORAES

IPC分类号： H01L43/12 ,  H01F41/34

CPC分类号： H01L43/12 ,  G11B5/746 ,  G11B5/855 ,  G11C11/16 ,  H01F41/34 ,  H01L21/2855 ,  H01L21/3081

摘要： A method and apparatus for forming a magnetic layer having a pattern of magnetic properties on a substrate is described. The method includes using a metal nitride hardmask layer to pattern the magnetic layer by plasma exposure. The metal nitride layer is patterned using a nanoimprint patterning process with a silicon oxide pattern negative material. The pattern is developed in the metal nitride using a halogen and oxygen containing remote plasma, and is removed after plasma exposure using a caustic wet strip process. All processing is done at low temperatures to avoid thermal damage to magnetic materials.

摘要翻译： 描述了在基板上形成具有磁特性图案的磁性层的方法和装置。 该方法包括使用金属氮化物硬掩模层通过等离子体曝光对磁性层进行图案化。 使用具有氧化硅图案负材料的纳米压印图案化工艺对金属氮化物层进行构图。 在使用含卤素和含氧远距离等离子体的金属氮化物中形成图案，并且在使用苛性湿法剥离法等离子体暴露后除去。 所有加工都是在低温下进行，以避免热损坏磁性材料。

公开(公告)号：US20140042016A1

公开(公告)日：2014-02-13

申请号：US14054477

申请日：2013-10-15

申请人： Applied Materials, Inc.

发明人： Yong CAO ,  Xianmin TANG ,  Srinivas GANDIKOTA ,  Wei D. WANG ,  Zhendong LIU ,  Kevin MORAES ,  Muhammad M. RASHEED ,  Thanh X. NGUYEN ,  Ananthkrishna JUPUDI

IPC分类号： H01L21/28 ,  H01L21/285

CPC分类号： H01L21/28079 ,  C23C14/165 ,  C23C14/345 ,  C23C14/35 ,  H01L21/28088 ,  H01L21/2855 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78

摘要： Embodiments described herein provide a semiconductor device and methods and apparatuses of forming the same. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions. In one embodiment, the method includes positioning a substrate within a processing chamber, wherein the substrate includes a source and drain region, a gate dielectric layer between the source and drain regions, and a conductive film layer on the gate dielectric layer. The method also includes depositing a refractory metal nitride film layer on the conductive film layer, depositing a silicon-containing film layer on the refractory metal nitride film layer, and depositing a tungsten film layer on the silicon-containing film layer.

摘要翻译： 本文所述的实施例提供了一种半导体器件及其形成方法和装置。 半导体器件包括在源极和漏极区域之间的衬底上具有源极和漏极区域以及栅电极堆叠的衬底。 在一个实施例中，该方法包括将衬底定位在处理室内，其中衬底包括源极和漏极区域，源极和漏极区域之间的栅极介电层以及栅极电介质层上的导电膜层。 该方法还包括在导电膜层上沉积难熔金属氮化物膜层，在难熔金属氮化物膜层上沉积含硅膜层，并在含硅膜层上沉积钨膜层。

公开(公告)号：US20200373183A1

公开(公告)日：2020-11-26

申请号：US16848645

申请日：2020-04-14

申请人： Applied Materials, Inc.

发明人： Alexander N. LERNER ,  Michael P. KARAZIM ,  Andrew J. CONSTANT ,  Jeffrey A. BRODINE ,  Kim Ramkumar VELLORE ,  Kevin MORAES ,  Roey SHAVIV

IPC分类号： H01L21/68 ,  H01J37/32 ,  C23C16/04 ,  H01L21/677 ,  H01L21/673

摘要： An alignment module for positioning a mask on a substrate comprises a mask stocker, an alignment stage, and a transfer robot. The mask stocker houses a mask cassette that stores a plurality of masks. The alignment stage is configured to support a carrier and a substrate. The transfer robot is configured to transfer one of the one or more masks from the mask stocker to the alignment stage and position the mask over the substrate. The alignment module may be part of an integrated platform having one or more transfer chambers, a factory interface having a substrate carrier chamber and one or more processing chambers. A carrier may be coupled to a substrate within the substrate carrier chamber and moved between the processing chambers to generate a semiconductor device.

公开(公告)号：US20200295265A1

公开(公告)日：2020-09-17

申请号：US16806511

申请日：2020-03-02

申请人： Applied Materials, Inc.

发明人： Kevin MORAES ,  Alexander N. LERNER

IPC分类号： H01L51/00 ,  C23C14/04 ,  C23C14/12 ,  C23C14/02

摘要： Generally, examples described herein relate to deposition masks and methods of manufacturing and using such deposition masks. An example includes a method for forming a deposition mask. A mask layer is deposited on a substrate. Mask openings are patterned through the mask layer. A central portion of the substrate is removed to define a substrate opening through a periphery portion of the substrate. The mask layer with the mask openings through the mask layer extending across the substrate opening.

公开(公告)号：US20190027403A1

公开(公告)日：2019-01-24

申请号：US16140342

申请日：2018-09-24

申请人： APPLIED MATERIALS, INC.

发明人： Sree Rangasai V. KESAPRAGADA ,  Kevin MORAES ,  Srinivas GUGGILLA ,  He REN ,  Mehul NAIK ,  David THOMPSON ,  Weifeng YE ,  Yana CHENG ,  Yong CAO ,  Xianmin TANG ,  Paul F. MA ,  Deenesh PADHI

IPC分类号： H01L21/768 ,  H01L21/02

CPC分类号： H01L21/76832 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834

摘要： In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

公开(公告)号：US20160260896A1

公开(公告)日：2016-09-08

申请号：US15157120

申请日：2016-05-17

申请人： Applied Materials, Inc.

发明人： Roman GOUK ,  Steven VERHAVERBEKE ,  Alexander KONTOS ,  Adolph Miller ALLEN ,  Kevin MORAES

IPC分类号： H01L43/12

CPC分类号： H01L43/12 ,  G11B5/746 ,  G11B5/855 ,  G11C11/16 ,  H01F41/34 ,  H01L21/2855 ,  H01L21/3081

摘要： A method and apparatus for forming a magnetic layer having a pattern of magnetic properties on a substrate is described. The method includes using a metal nitride hardmask layer to pattern the magnetic layer by plasma exposure. The metal nitride layer is patterned using a nanoimprint patterning process with a silicon oxide pattern negative material. The pattern is developed in the metal nitride using a halogen and oxygen containing remote plasma, and is removed after plasma exposure using a caustic wet strip process. All processing is done at low temperatures to avoid thermal damage to magnetic materials.

公开(公告)号：US20240218503A1

公开(公告)日：2024-07-04

申请号：US18608005

申请日：2024-03-18

申请人： Applied Materials, Inc.

发明人： Sang-Ho YU ,  Kevin MORAES ,  Seshadri GANGULI ,  Hua CHUNG ,  See-Eng PHAN

IPC分类号： C23C16/16 ,  C23C16/02 ,  C23C16/18 ,  C23C16/455 ,  C23C16/50 ,  H01L21/02 ,  H01L21/285 ,  H01L21/324 ,  H01L21/768

CPC分类号： C23C16/16 ,  C23C16/0218 ,  C23C16/0245 ,  C23C16/18 ,  C23C16/4554 ,  C23C16/45542 ,  C23C16/50 ,  H01L21/02068 ,  H01L21/02074 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/324 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76862 ,  H01L21/76883

摘要： Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface. In another embodiment, a deposition-treatment cycle includes performing the vapor deposition process and subsequently a post-treatment process, which deposition-treatment cycle may be repeated to form multiple cobalt capping layers.