公开(公告)号：US20180218902A1

公开(公告)日：2018-08-02

申请号：US15882204

申请日：2018-01-29

Applicant: Applied Materials, Inc.

Inventor： Eswaranand VENKATASUBRAMANIAN ,  Abhijit Basu MALLICK ,  Susmit Singha ROY ,  Takehito KOSHIZAWA

IPC: H01L21/033 ,  H01L21/02 ,  C23C16/32 ,  C23C16/34 ,  C23C16/50

CPC classification number: H01L21/0332 ,  C23C16/0272 ,  C23C16/32 ,  C23C16/342 ,  C23C16/345 ,  C23C16/50 ,  C23C16/505 ,  H01L21/02175 ,  H01L21/02205 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31111 ,  H01L21/31122 ,  H01L21/31144

Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of hardmask films on a substrate. In one implementation, a method of forming a hardmask layer on a substrate is provided. The method comprises forming a seed layer on a substrate by supplying a seed layer gas mixture in a processing chamber. The method further includes forming a transition layer comprising tungsten, boron and carbon on the seed layer by supplying a transition layer gas mixture in the processing chamber. The method further includes forming a bulk hardmask layer comprising tungsten, boron and carbon on the transition layer by supplying a main deposition gas mixture in the processing chamber.

公开(公告)号：US20240339316A1

公开(公告)日：2024-10-10

申请号：US18746799

申请日：2024-06-18

Applicant: Applied Materials, Inc.

Inventor： Aykut AYDIN ,  Rui CHENG ,  Karthik JANAKIRAMAN ,  Abhijit Basu MALLICK ,  Takehito KOSHIZAWA ,  Bo QI

IPC: H01L21/02

CPC classification number: H01L21/02123 ,  H01L21/02211 ,  H01L21/02271

Abstract: Embodiments of the present disclosure generally relate to processes for forming silicon- and boron-containing films for use in, e.g., spacer-defined patterning applications. In an embodiment, a spacer-defined patterning process is provided. The process includes disposing a substrate in a processing volume of a processing chamber, the substrate having patterned features formed thereon, and flowing a first process gas into the processing volume, the first process gas comprising a silicon-containing species, the silicon-containing species having a higher molecular weight than SiH4. The process further includes flowing a second process gas into the processing volume, the second process gas comprising a boron-containing species, and depositing, under deposition conditions, a conformal film on the patterned features, the conformal film comprising silicon and boron.

公开(公告)号：US20150079799A1

公开(公告)日：2015-03-19

申请号：US14029771

申请日：2013-09-17

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. NEMANI ,  Praburam GOPALRAJA ,  Takehito KOSHIZAWA

IPC: H01L21/3065

CPC classification number: H01L21/31116 ,  H01J37/32082 ,  H01J37/32357 ,  H01J37/32449 ,  H01J2237/334 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L2221/1063

Abstract: Methods for etching a dielectric barrier layer disposed on the substrate using a low temperature etching process along with a subsequent interface protection layer deposition process are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes transferring a substrate having a dielectric barrier layer disposed thereon into an etching processing chamber, performing a treatment process on the dielectric barrier layer, remotely generating a plasma in an etching gas mixture supplied into the etching processing chamber to etch the treated dielectric barrier layer disposed on the substrate, plasma annealing the dielectric barrier layer to remove the dielectric barrier layer from the substrate, and forming an interface protection layer after the dielectric barrier is removed from the substrate.

Abstract translation: 提供了使用低温蚀刻工艺以及随后的界面保护层沉积工艺来蚀刻设置在基板上的电介质阻挡层的方法。 在一个实施例中，用于蚀刻设置在基板上的电介质阻挡层的方法包括将其上设置有介电阻挡层的基板转印到蚀刻处理室中，对介电阻挡层进行处理工艺，在蚀刻中远程产生等离子体 气体混合物供应到蚀刻处理室中以蚀刻设置在基板上的经处理的介电阻挡层，等离子体对介电阻挡层进行退火以从基板移除电介质阻挡层，并且在介电阻挡层从基板去除之后形成界面保护层 基质。

公开(公告)号：US20230021761A1

公开(公告)日：2023-01-26

申请号：US17961224

申请日：2022-10-06

Applicant: Applied Materials, Inc.

Inventor： Eswaranand VENKATASUBRAMANIAN ,  Yang YANG ,  Pramit MANNA ,  Kartik RAMASWAMY ,  Takehito KOSHIZAWA ,  Abhijit Basu MALLICK

IPC: H01L21/02 ,  C23C16/26 ,  H01L21/033

Abstract: Embodiments herein provide methods of depositing an amorphous carbon layer using a plasma enhanced chemical vapor deposition (PECVD) process and hard masks formed therefrom. In one embodiment, a method of processing a substrate includes positioning a substrate on a substrate support, the substrate support disposed in a processing volume of a processing chamber, flowing a processing gas comprising a hydrocarbon gas and a diluent gas into the processing volume, maintaining the processing volume at a processing pressure less than about 100 mTorr, igniting and maintaining a deposition plasma of the processing gas by applying a first power to one of one or more power electrodes of the processing chamber, maintaining the substrate support at a processing temperature less than about 350° C., exposing a surface of the substrate to the deposition plasma, and depositing an amorphous carbon layer on the surface of the substrate.

公开(公告)号：US20150262869A1

公开(公告)日：2015-09-17

申请号：US14276879

申请日：2014-05-13

Applicant: APPLIED MATERIALS, INC.

Inventor： Mehul B. NAIK ,  Srinivas D. NEMANI ,  Takehito KOSHIZAWA ,  He REN

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3213

CPC classification number: H01L21/32136 ,  H01J37/321 ,  H01J37/32357 ,  H01J37/3244 ,  H01L21/02071 ,  H01L21/02274 ,  H01L21/32139 ,  H01L21/67184 ,  H01L21/67207 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76885

Abstract: Embodiments of the present invention provide methods for forming an interconnection structure in semiconductor devices without breaking vacuum with minimum oxidation/atmosphere exposure. In one embodiment, a method for forming an interconnection structure for semiconductor devices includes supplying a barrier layer etching gas mixture into a first processing chamber having a substrate disposed therein to etch portions of a barrier layer exposed by a patterned metal layer until the underlying substrate is exposed, the first processing chamber disposed in a processing system, and forming a liner layer on the substrate covering the etched barrier layer in a second processing chamber disposed in the processing system.

Abstract translation: 本发明的实施例提供了在半导体器件中形成互连结构而不破坏最小氧化/大气暴露的真空的方法。 在一个实施例中，用于形成用于半导体器件的互连结构的方法包括将阻挡层蚀刻气体混合物供应到具有设置在其中的衬底的第一处理室中，以蚀刻由图案化金属层暴露的阻挡层的部分，直到下面的衬底为 暴露的第一处理室，设置在处理系统中，并且在布置在处理系统中的第二处理室中，在覆盖蚀刻的阻挡层的基板上形成衬垫层。

公开(公告)号：US20220013359A1

公开(公告)日：2022-01-13

申请号：US17459839

申请日：2021-08-27

Applicant: Applied Materials, Inc.

Inventor： Takehito KOSHIZAWA ,  Rui CHENG ,  Tejinder SINGH ,  Hidetaka OSHIO

IPC: H01L21/033 ,  H01L21/311

Abstract: In an embodiment, a method for forming features for semiconductor processing. A first mandrel and a second mandrel are formed on a substrate. A first spacer is formed along a first sidewall of the first mandrel, and a second spacer is formed along a second sidewall of the second mandrel. A gap is defined between the first spacer and the second spacer. The gap is filled by a gap-filling material. In some examples, the gap-filling material includes a doped silicon material. In some examples, the first spacer and the second spacer each include a doped silicon material.

公开(公告)号：US20210043449A1

公开(公告)日：2021-02-11

申请号：US17045453

申请日：2019-04-08

Applicant: Applied Materials, Inc.

Inventor： Eswaranand VENKATASUBRAMANIAN ,  Yang YANG ,  Pramit MANNA ,  Kartik RAMASWAMY ,  Takehito KOSHIZAWA ,  Abhijit Basu MALLICK

IPC: H01L21/02 ,  C23C16/26 ,  H01L21/033

Abstract: Embodiments herein provide methods of depositing an amorphous carbon layer using a plasma enhanced chemical vapor deposition (PECVD) process and hard masks formed therefrom. In one embodiment, a method of processing a substrate includes positioning a substrate on a substrate support, the substrate support disposed in a processing volume of a processing chamber, flowing a processing gas comprising a hydrocarbon gas and a diluent gas into the processing volume, maintaining the processing volume at a processing pressure less than about 100 mTorr, igniting and maintaining a deposition plasma of the processing gas by applying a first power to one of one or more power electrodes of the processing chamber, maintaining the substrate support at a processing temperature less than about 350° C., exposing a surface of the substrate to the deposition plasma, and depositing an amorphous carbon layer on the surface of the substrate.

公开(公告)号：US20210040618A1

公开(公告)日：2021-02-11

申请号：US16982955

申请日：2018-10-16

Applicant: Applied Materials, Inc.

Inventor： Eswaranand VENKATASUBRAMANIAN ,  Yang YANG ,  Pramit MANNA ,  Kartik RAMASWAMY ,  Takehito KOSHIZAWA ,  Abhijit B. MALLICK

IPC: C23C16/503 ,  H01L21/02 ,  C23C16/505 ,  C23C16/458 ,  C23C16/455 ,  C23C16/52

Abstract: Embodiments of the present disclosure relate to methods for depositing an amorphous carbon layer onto a substrate, including over previously formed layers on the substrate, using a plasma-enhanced chemical vapor deposition (PECVD) process, in particular, the methods described herein utilize a combination of RF AC power and pulsed DC power to create a plasma which deposits an amorphous carbon layer with power to create a plasma which deposits an amorphour carbon layer with a high ratio of sp3 (diamond-like) carbon to sp2 (graphite-like) carbon. The methods also provide for lower processing pressures, lower processing temperatures, and higher processing powers, each of which, alone or in combination, may further increase the relative fraction of sp3 carbon in the deposited amorphous carbon layer. As a result of the higher sp3 carbon fraction, the methods described herein provide amorphous carbon layers having improved density, rigidity, etch selectivity, and film stress as compared to amorphous carbon layers deposited by conventional methods.

公开(公告)号：US20230220551A1

公开(公告)日：2023-07-13

申请号：US18119406

申请日：2023-03-09

Applicant: Applied Materials, Inc.

Inventor： Eswaranand VENKATASUBRAMANIAN ,  Yang YANG ,  Pramit MANNA ,  Kartik RAMASWAMY ,  Takehito KOSHIZAWA ,  Abhijit B. MALLICK

IPC: C23C16/503 ,  C23C16/458 ,  H01L21/02 ,  C23C16/52 ,  C23C16/505 ,  C23C16/455

CPC classification number: C23C16/503 ,  C23C16/4586 ,  H01L21/02274 ,  C23C16/52 ,  C23C16/505 ,  C23C16/45502 ,  H01L21/02521 ,  H01L21/02115

Abstract: Embodiments of the present disclosure relate to methods for depositing an amorphous carbon layer onto a substrate, including over previously formed layers on the substrate, using a plasma-enhanced chemical vapor deposition (PECVD) process. In particular, the methods described herein utilize a combination of RF AC power and pulsed DC power to create a plasma which deposits an amorphous carbon layer with a high ratio of sp3 (diamond-like) carbon to sp2 (graphite-like) carbon. The methods also provide for lower processing pressures, lower processing temperatures, and higher processing powers, each of which, alone or in combination, may further increase the relative fraction of sp3 carbon in the deposited amorphous carbon layer. As a result of the higher sp3 carbon fraction, the methods described herein provide amorphous carbon layers having improved density, rigidity, etch selectivity, and film stress as compared to amorphous carbon layers deposited by conventional methods.

公开(公告)号：US20220406594A1

公开(公告)日：2022-12-22

申请号：US17352039

申请日：2021-06-18

Applicant: Applied Materials, Inc.

Inventor： Aykut AYDIN ,  Rui CHENG ,  Karthik JANAKIRAMAN ,  Abhijit B. MALLICK ,  Takehito KOSHIZAWA ,  Bo QI

IPC: H01L21/02

Abstract: Embodiments of the present disclosure generally relate to processes for forming silicon- and boron-containing films for use in, e.g., spacer-defined patterning applications. In an embodiment, a spacer-defined patterning process is provided. The process includes disposing a substrate in a processing volume of a processing chamber, the substrate having patterned features formed thereon, and flowing a first process gas into the processing volume, the first process gas comprising a silicon-containing species, the silicon-containing species having a higher molecular weight than SiH4. The process further includes flowing a second process gas into the processing volume, the second process gas comprising a boron-containing species, and depositing, under deposition conditions, a conformal film on the patterned features, the conformal film comprising silicon and boron.