摘要:
A submount for a light emitting device package includes a substrate. A first bond pad and a second bond pad are on a first surface of the substrate. The first bond pad includes a die attach region offset toward a first end of the substrate and configured to receive a light emitting diode thereon. The second bond pad includes a bonding region between the first bond pad and the second end of the substrate and a second bond pad extension that extends from the bonding region along a side of the substrate toward a corner of the substrate at the first end of the substrate. First and second solder pads are a the second surface of the substrate. The first solder pad is adjacent the first end of the substrate and contacts the second bond pad. The second solder pad is adjacent the second end of the substrate and contacts the first bond pad. Related LED packages and methods of forming LED packages are disclosed.
摘要:
A submount for a light emitting device package includes a substrate. A first bond pad and a second bond pad are on a first surface of the substrate. The first bond pad includes a die attach region offset toward a first end of the substrate and configured to receive a light emitting diode thereon. The second bond pad includes a bonding region between the first bond pad and the second end of the substrate and a second bond pad extension that extends from the bonding region along a side of the substrate toward a corner of the substrate at the first end of the substrate. First and second solder pads are a the second surface of the substrate. The first solder pad is adjacent the first end of the substrate and contacts the second bond pad. The second solder pad is adjacent the second end of the substrate and contacts the first bond pad. Related LED packages and methods of forming LED packages are disclosed.
摘要:
A submount for a light emitting device package includes a rectangular substrate. A first bond pad and a second bond pad are on a first surface of the substrate. The first bond pad includes a die attach region offset toward a first end of the substrate and configured to receive a light emitting diode thereon. The second bond pad includes a bonding region between the first bond pad and the second end of the substrate and a second bond pad extension that extends from the bonding region along a side of the substrate toward a corner of the substrate at the first end of the substrate. First and second solder pads are a the second surface of the substrate. The first solder pad is adjacent the first end of the substrate and contacts the second bond pad. The second solder pad is adjacent the second end of the substrate and contacts the first bond pad. Related LED packages and methods of forming LED packages are disclosed.
摘要:
A submount for a light emitting device package includes a rectangular substrate. A first bond pad and a second bond pad are on a first surface of the substrate. The first bond pad includes a die attach region offset toward a first end of the substrate and configured to receive a light emitting diode thereon. The second bond pad includes a bonding region between the first bond pad and the second end of the substrate and a second bond pad extension that extends from the bonding region along a side of the substrate toward a corner of the substrate at the first end of the substrate. First and second solder pads are a the second surface of the substrate. The first solder pad is adjacent the first end of the substrate and contacts the second bond pad. The second solder pad is adjacent the second end of the substrate and contacts the first bond pad. Related LED packages and methods of forming LED packages are disclosed.
摘要:
A method for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs, typically on a wafer, and coating the LEDs with a conversion material so that at least some light from the LEDs passes through the conversion material and is converted. The light emission from the LED chips comprises light from the conversion material, typically in combination with LED light. The emission characteristics of at least some of the LED chips is measured and at least some of the conversion material over the LEDs is removed to alter the emission characteristics of the LED chips. The invention is particularly applicable to fabricating LED chips on a wafer where the LED chips have light emission characteristics that are within a range of target emission characteristics. This target range can fall within an emission region on a CIE curve to reduce the need for binning of the LEDs from the wafer. The emission characteristics of the LED chips in the wafer can be tuned to the desired range by micro-machining the conversion material over the LEDs.
摘要:
A light emitting device includes a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer. A non-transparent feature, such as a wire bond pad, is on the p-type semiconductor layer or on the n-type semiconductor layer opposite the p-type semiconductor layer, and a reduced conductivity region is in the p-type semiconductor layer or the n-type semiconductor layer and is aligned with the non-transparent feature. The reduced conductivity region may extend from a surface of the p-type semiconductor layer opposite the n-type semiconductor layer towards the active region and/or from a surface of the n-type semiconductor layer opposite the p-type semiconductor layer towards the active region.
摘要:
A light emitting device includes a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer. A non-transparent feature, such as a wire bond pad, is on the p-type semiconductor layer or on the n-type semiconductor layer opposite the p-type semiconductor layer, and a reduced conductivity region is in the p-type semiconductor layer or the n-type semiconductor layer and is aligned with the non-transparent feature. The reduced conductivity region may extend from a surface of the p-type semiconductor layer opposite the n-type semiconductor layer towards the active region and/or from a surface of the n-type semiconductor layer opposite the p-type semiconductor layer towards the active region.