公开(公告)号：US20180277512A1

公开(公告)日：2018-09-27

申请号：US15464920

申请日：2017-03-21

申请人： Bernd Waidhas ,  Georg Seidemann ,  Andreas Wolter ,  Thomas Wagner ,  Stephan Stoeckl ,  Laurent Millou

发明人： Bernd Waidhas ,  Georg Seidemann ,  Andreas Wolter ,  Thomas Wagner ,  Stephan Stoeckl ,  Laurent Millou

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

摘要： An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module.

公开(公告)号：US20180190589A1

公开(公告)日：2018-07-05

申请号：US15394388

申请日：2016-12-29

申请人： Bernd Waidhas ,  Stephan Stoeckl ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Georg Seidemann ,  Thomas Wagner ,  Laurent Millou

发明人： Bernd Waidhas ,  Stephan Stoeckl ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Georg Seidemann ,  Thomas Wagner ,  Laurent Millou

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L23/053

CPC分类号： H01L23/5386 ,  H01L21/4846 ,  H01L23/053 ,  H01L23/5387 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15738 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/13099

摘要： A bent-bridge semiconductive apparatus includes a silicon bridge that is integral to a semiconductive device and the silicon bridge is deflected out of planarity. The silicon bridge may couple two semiconductive devices, all of which are from an integral processed die.

公开(公告)号：US20190006281A1

公开(公告)日：2019-01-03

申请号：US15637641

申请日：2017-06-29

申请人： Georg Seidemann ,  Bernd Waidhas ,  Thomas Wagner ,  Andreas Wolter ,  Laurent Millou

发明人： Georg Seidemann ,  Bernd Waidhas ,  Thomas Wagner ,  Andreas Wolter ,  Laurent Millou

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L25/065 ,  G11C16/18

CPC分类号： H01L23/5382 ,  G11C16/18 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/4826 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92225 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15313

摘要： A multi-chip module includes two silicon bridge interconnects and three components that are tied together by the bridges with one of the components in the center. At least one of the silicon bridge interconnects is bent to create a non-planar chip-module form factor. Cross-connected multi-chip silicon bent-bridge interconnect modules include the two silicon bridges contacting the center component at right angles to each other, plus a fourth component and a third silicon bridge interconnect contacting the fourth component and any one of the original three components.

公开(公告)号：US20180284851A1

公开(公告)日：2018-10-04

申请号：US15475368

申请日：2017-03-31

申请人： Georg Seidemann ,  Bernd Waidhas ,  Thomas Wagner ,  Andreas Wolter ,  Sonja Koller ,  Vishnu Prasad

发明人： Georg Seidemann ,  Bernd Waidhas ,  Thomas Wagner ,  Andreas Wolter ,  Sonja Koller ,  Vishnu Prasad

IPC分类号： G06F1/20 ,  H05K7/20 ,  G06F1/18

摘要： An electronic component assembly includes a substrate having a first face and an opposed second face. One or more electronic components are coupled with either or both of the first and second faces. A filler interface heat transfer system is coupled with the substrate. The filler interface heat transfer system includes at least one enclosure shell coupled with one of the first or second faces. The at least one enclosure shell surrounds a filler cavity including the one or more electronic components therein. A heat transfer filler is within the filler cavity, the heat transfer filler includes a contoured filler profile conforming to at least the one or more electronic components.

公开(公告)号：US20180096970A1

公开(公告)日：2018-04-05

申请号：US15282855

申请日：2016-09-30

申请人： Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Thomas Wagner ,  Bernd Waidhas

发明人： Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Thomas Wagner ,  Bernd Waidhas

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L24/06 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/02311 ,  H01L2224/0237 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/06132 ,  H01L2224/06134 ,  H01L2224/09177 ,  H01L2224/11334 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16145 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/73204 ,  H01L2225/1058 ,  H01L2225/1064

摘要： A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.

公开(公告)号：US20200006272A1

公开(公告)日：2020-01-02

申请号：US16024413

申请日：2018-06-29

申请人： Andreas Augustin ,  Georg Seidemann ,  Thomas Wagner ,  Bernd Waidhas

发明人： Andreas Augustin ,  Georg Seidemann ,  Thomas Wagner ,  Bernd Waidhas

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L21/768

摘要： Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

公开(公告)号：US20180286798A1

公开(公告)日：2018-10-04

申请号：US15476270

申请日：2017-03-31

申请人： Bernd Waidhas ,  Sonja Koller ,  Georg Seidemann

发明人： Bernd Waidhas ,  Sonja Koller ,  Georg Seidemann

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L29/7835 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/06 ,  H01L29/66659

摘要： A power mesh-on-die apparatus includes a solder trace that enhances current flow for a power source trace between adjacent power bumps. The solder trace is also applied between power drain bumps on a power drain trace.

公开(公告)号：US20190252792A1

公开(公告)日：2019-08-15

申请号：US15892632

申请日：2018-02-09

申请人： Saravana Maruthamuthu ,  Bernd Waidhas ,  Andreas Augustin ,  Georg Seidemann

发明人： Saravana Maruthamuthu ,  Bernd Waidhas ,  Andreas Augustin ,  Georg Seidemann

IPC分类号： H01Q19/06 ,  H01Q1/48 ,  H01Q15/08 ,  H01L23/66 ,  H01L23/528 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/768 ,  H01L23/13

CPC分类号： H01Q19/06 ,  H01L21/32051 ,  H01L21/4846 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/66 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16227 ,  H01L2224/81801 ,  H01L2924/142 ,  H01Q1/48 ,  H01Q15/08

摘要： Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.

公开(公告)号：US20190214327A1

公开(公告)日：2019-07-11

申请号：US15866810

申请日：2018-01-10

申请人： Sonja Koller ,  Bernd Waidhas ,  Thomas Ort ,  Andreas Wolter

发明人： Sonja Koller ,  Bernd Waidhas ,  Thomas Ort ,  Andreas Wolter

IPC分类号： H01L23/373 ,  H01L21/56 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L23/3733 ,  H01L21/56 ,  H01L23/49816 ,  H01L24/49 ,  H01L25/0657

摘要： A semiconductor device includes a semiconductor die that is coupled to a substrate. A mold compound encapsulates the semiconductor die and one or more passages are in the mold compound between a backside of the mold compound and an electrically non-active region of the first semiconductor die. A thermal conductor material within the one or more of the passages.

公开(公告)号：US08415803B2

公开(公告)日：2013-04-09

申请号：US12871939

申请日：2010-08-31

申请人： Thorsten Meyer ,  Gottfried Beer ,  Christian Geissler ,  Thomas Ort ,  Klaus Pressel ,  Bernd Waidhas ,  Andreas Wolter

发明人： Thorsten Meyer ,  Gottfried Beer ,  Christian Geissler ,  Thomas Ort ,  Klaus Pressel ,  Bernd Waidhas ,  Andreas Wolter

IPC分类号： H01L23/48 ,  H01L21/768

摘要： A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.