公开(公告)号：US20120138769A1

公开(公告)日：2012-06-07

申请号：US13371840

申请日：2012-02-13

申请人： Bing Dang ,  Peter A. Gruber ,  Luc Guerin ,  Chirag S. Patel

发明人： Bing Dang ,  Peter A. Gruber ,  Luc Guerin ,  Chirag S. Patel

IPC分类号： B22C9/22

CPC分类号： B23K1/0016 ,  B23K3/0623 ,  B23K2101/40 ,  H01L24/11 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/16225 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/29099 ,  H01L2924/00

摘要： Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.

摘要翻译： 通过执行几个步骤在晶片的附接点上形成互连。 在半导体衬底中形成具有预定形状的多个空腔。 然后用互连材料填充这些空腔以形成互连。 互连随后连接到晶片的附接点。

公开(公告)号：US20090072392A1

公开(公告)日：2009-03-19

申请号：US11856831

申请日：2007-09-18

申请人： Bing Dang ,  Peter A. Gruber ,  Luc Guerin ,  Chirag S. Patel

发明人： Bing Dang ,  Peter A. Gruber ,  Luc Guerin ,  Chirag S. Patel

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： B23K1/0016 ,  B23K3/0623 ,  B23K2101/40 ,  H01L24/11 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/16225 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/29099 ,  H01L2924/00

摘要： Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.

摘要翻译： 通过执行几个步骤在晶片的附接点上形成互连。 在半导体衬底中形成具有预定形状的多个空腔。 然后用互连材料填充这些空腔以形成互连。 互连随后连接到晶片的附接点。

公开(公告)号：US08328156B2

公开(公告)日：2012-12-11

申请号：US13371840

申请日：2012-02-13

申请人： Bing Dang ,  Peter A. Gruber ,  Luc Guerin ,  Chirag S. Patel

发明人： Bing Dang ,  Peter A. Gruber ,  Luc Guerin ,  Chirag S. Patel

IPC分类号： B28B7/22 ,  E04G11/50

CPC分类号： B23K1/0016 ,  B23K3/0623 ,  B23K2101/40 ,  H01L24/11 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/16225 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/29099 ,  H01L2924/00

摘要： Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.

摘要翻译： 通过执行几个步骤在晶片的附接点上形成互连。 在半导体衬底中形成具有预定形状的多个空腔。 然后用互连材料填充这些空腔以形成互连。 互连随后连接到晶片的附接点。

公开(公告)号：US08148255B2

公开(公告)日：2012-04-03

申请号：US11856831

申请日：2007-09-18

申请人： Bing Dang ,  Peter A. Gruber ,  Luc Guerin ,  Chirag S. Patel

发明人： Bing Dang ,  Peter A. Gruber ,  Luc Guerin ,  Chirag S. Patel

IPC分类号： H01L21/44

CPC分类号： B23K1/0016 ,  B23K3/0623 ,  B23K2101/40 ,  H01L24/11 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/16225 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/29099 ,  H01L2924/00

摘要： Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.

公开(公告)号：US20110044369A1

公开(公告)日：2011-02-24

申请号：US12544696

申请日：2009-08-20

申请人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chirag S. Patel

发明人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chirag S. Patel

IPC分类号： H01S5/18 ,  H01L31/0232 ,  H01L23/34 ,  H01L21/50

CPC分类号： H01L27/1446 ,  G02B6/4204 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/367 ,  H01L25/16 ,  H01L27/14625 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01S5/005 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02407 ,  H01S5/02476 ,  H01S5/183 ,  H01S5/423 ,  H01L2924/014 ,  H01L2924/00

摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

摘要翻译： 公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。 硅层具有允许光通过的光通孔。 光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。 多个OE元件耦合到硅层并与布线电连通。 至少一个OE元件被定位成与用于接收光的光通孔光学对准。 载体介于电互连元件之间。 载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

公开(公告)号：US08290008B2

公开(公告)日：2012-10-16

申请号：US12544696

申请日：2009-08-20

申请人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chirag S. Patel

发明人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chirag S. Patel

IPC分类号： H01S5/022 ,  H01S5/024

CPC分类号： H01L27/1446 ,  G02B6/4204 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/367 ,  H01L25/16 ,  H01L27/14625 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01S5/005 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02407 ,  H01S5/02476 ,  H01S5/183 ,  H01S5/423 ,  H01L2924/014 ,  H01L2924/00

摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

摘要翻译： 公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。 硅层具有允许光通过的光通孔。 光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。 多个OE元件耦合到硅层并与布线电连通。 至少一个OE元件被定位成与用于接收光的光通孔光学对准。 载体介于电互连元件之间。 载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

公开(公告)号：US20120326290A1

公开(公告)日：2012-12-27

申请号：US13604341

申请日：2012-09-05

申请人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

发明人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

IPC分类号： H01L23/34 ,  H01L21/50

CPC分类号： H01L27/1446 ,  G02B6/4204 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/367 ,  H01L25/16 ,  H01L27/14625 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01S5/005 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02407 ,  H01S5/02476 ,  H01S5/183 ,  H01S5/423 ,  H01L2924/014 ,  H01L2924/00

摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

摘要翻译： 公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。 硅层具有允许光通过的光通孔。 光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。 多个OE元件耦合到硅层并与布线电连通。 至少一个OE元件被定位成与用于接收光的光通孔光学对准。 载体介于电互连元件之间。 载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

公开(公告)号：US08559474B2

公开(公告)日：2013-10-15

申请号：US13604341

申请日：2012-09-05

申请人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank F. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

发明人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank F. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

IPC分类号： H01S5/024 ,  H01S5/18 ,  H01L23/28 ,  H01L23/18

CPC分类号： H01L27/1446 ,  G02B6/4204 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/367 ,  H01L25/16 ,  H01L27/14625 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01S5/005 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02407 ,  H01S5/02476 ,  H01S5/183 ,  H01S5/423 ,  H01L2924/014 ,  H01L2924/00

摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

摘要翻译： 公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。 硅层具有允许光通过的光通孔。 光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。 多个OE元件耦合到硅层并与布线电连通。 至少一个OE元件被定位成与用于接收光的光通孔光学对准。 载体介于电互连元件之间。 载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

公开(公告)号：US08383505B2

公开(公告)日：2013-02-26

申请号：US13080105

申请日：2011-04-05

申请人： Luc Guerin ,  Mario J. Interrante ,  Michael J. Shapiro ,  Thuy Tran-Quinn ,  Van T. Truong

发明人： Luc Guerin ,  Mario J. Interrante ,  Michael J. Shapiro ,  Thuy Tran-Quinn ,  Van T. Truong

IPC分类号： H01L21/00

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05681 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2224/05552

摘要： A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

摘要翻译： 焊球接触和制造焊球接触的方法包括：在集成电路（IC）芯片和金属焊盘上形成有通孔的第一绝缘层; 设置在所述通孔内和所述第一绝缘层的围绕所述通孔的部分上的凸块下冶金（UBM）结构; 第二绝缘层，形成在所述UBM结构的位于所述通孔的中心的外部的上表面上; 以及填充通孔并且设置在UBM结构的与通孔接触的内部的上表面上方的焊球，其中在焊球下面的UBM结构具有比焊球更大的直径。

公开(公告)号：US20090123589A1

公开(公告)日：2009-05-14

申请号：US11939604

申请日：2007-11-14

申请人： Eric Bouchard ,  Luc Guerin ,  Robert G. Haas

发明人： Eric Bouchard ,  Luc Guerin ,  Robert G. Haas

IPC分类号： B28B17/00

CPC分类号： C03C19/00 ,  Y10T409/303808

摘要： An exemplary method for marking molds, the method comprising, configuring a milling machine to operate with a diamond coated bit having an angle of approximately 60 degrees, and engraving a unique identifier on a bottom surface of a borosilicate glass injection molded soldering mold with the milling machine.

摘要翻译： 一种用于标记模具的示例性方法，所述方法包括：将铣床配置成与具有约60度角度的金刚石涂层钻头一起操作，以及在硼硅酸盐玻璃注射成型焊接模具的底表面上雕刻独特的标识符，其中铣削 机。