公开(公告)号：US20170358459A1

公开(公告)日：2017-12-14

申请号：US15523742

申请日：2015-11-09

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA

Inventor： Shay REBOH ,  Laurent GRENOUILLET ,  Yves MORAND

IPC: H01L21/308 ,  H01L21/311 ,  H01L27/12

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/1203

Abstract: A method for producing at least one pattern in a layer resting on a substrate, including: a) making amorphous at least one first block of an upper layer of crystalline material resting on a first amorphous supporting layer, while the crystalline structure of a second block of the upper layer that adjoins and is juxtaposed with the first block is preserved; b) partially recrystallizing the first block by using at least one side surface of the second block that is in contact with the first block as an area for the start of a recrystallization front, the partial recrystallization being carried out to preserve a region of amorphous material in the first block; c) selectively etching the amorphous material of the upper layer with respect to the crystalline material of the upper layer to form at least one first pattern in the upper layer.

公开(公告)号：US20170076997A1

公开(公告)日：2017-03-16

申请号：US15261226

申请日：2016-09-09

Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives

Inventor： Shay REBOH ,  Laurent GRENOUILLET ,  Frederic MILESI ,  Yves MORAND ,  Francois RIEUTORD

IPC: H01L21/84 ,  H01L21/265 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/266 ,  H01L21/02

CPC classification number: H01L21/84 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/7846

Abstract: Method for creation of stressed channel structure transistors wherein at least one amorphising ion implantation of the surface layer of a substrate of the semiconductor-on-insulator type is carried out through openings in a mask, so as to render zones of the surface layers amorphous and to induce relaxation of a zone intended to form a channel and located between the zones that have been rendered amorphous, the relaxation being carried out in a direction orthogonal to that in which it is intended that the channel current flows.

Abstract translation: 用于产生应力通道结构晶体管的方法，其中通过掩模中的开口进行绝缘体上半导体类型的衬底的表面层的至少一个非晶化离子注入，以使表面层的区域成为无定形和 以诱导旨在形成通道并且位于已经呈现无定形的区域之间的区域的松弛，该弛豫在与通道电流流动的方向正交的方向上进行。

公开(公告)号：US20160181155A1

公开(公告)日：2016-06-23

申请号：US14976958

申请日：2015-12-21

Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives

Inventor： Fabien DEPRAT ,  Perrine BATUDE ,  Yves MORAND ,  Heimanu NIEBOJEWKSI ,  Nicolas POSSEME

IPC: H01L21/768

CPC classification number: H01L21/76831 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/8221 ,  H01L27/0688

Abstract: Method of making an integrated circuit, comprising at least the following steps:a) form a first semiconducting or conducting element, covered with a first insulating layer on which there is a second semiconducting or conducting element, covered with a second insulating layer;b) form an opening passing through at least the second insulating layer, exposing a portion of the second element and opening up at least partly on the second element or adjacent to the second element;c) form a spacer located at the second element and comprising at least one dielectric material located at least between the second element and the opening;d) prolong the opening through the first insulating layer as far as the first element; ande) fill the opening with at least one conducting material, so as to form a contact.FIG 1G.

Abstract translation: 制造集成电路的方法，至少包括以下步骤：a）形成第一半导体或导电元件，其被第一绝缘层覆盖，其上存在第二绝缘层，第二绝缘层被第二绝缘层覆盖; b）形成通过至少所述第二绝缘层的开口，暴露所述第二元件的一部分并且至少部分地在所述第二元件上或邻近所述第二元件开口; c）形成位于所述第二元件处的间隔件，并且包括至少一个位于所述第二元件和所述开口之间的电介质材料; d）延长穿过第一绝缘层的开口，直到第一元件; 和e）用至少一种导电材料填充开口，以形成接触。 图1G。

公开(公告)号：US20200343374A1

公开(公告)日：2020-10-29

申请号：US16854968

申请日：2020-04-22

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Jean-Pierre COLINGE ,  Yves MORAND

IPC: H01L29/66

Abstract: Method for making a transistor, comprising: making, on a substrate, a gate surrounded by a dielectric material; depositing a stop layer on the gate and the dielectric material; etching the stop layer in accordance with an active region pattern, forming a channel location located on the gate; etching the dielectric material located in the active region pattern, forming source and drain locations; depositing a semimetal material in the channel, source and drain locations; planarizing the semimetal material; crystallizing the semimetal material, forming the channel and the source and drain; and wherein the semimetal material of the channel is semiconductive and the semimetal material of the source and drain is electrically conductive.

公开(公告)号：US20190244869A1

公开(公告)日：2019-08-08

申请号：US16230192

申请日：2018-12-21

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Cyrille LE ROYER ,  Yves MORAND

IPC: H01L21/84 ,  C23C16/34 ,  C23C14/06 ,  C23C14/48 ,  C23C28/04 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/223 ,  H01L29/78

CPC classification number: H01L21/84 ,  C23C14/0652 ,  C23C14/48 ,  C23C16/345 ,  C23C28/04 ,  H01L21/02118 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/2236 ,  H01L21/31155 ,  H01L21/823807 ,  H01L29/7843

Abstract: There is provided a method for producing, on one same plate, at least one first transistor surmounted at least partially on a voltage stressed layer and a second transistor surmounted at least partially on a compression stressed layer, the method including providing a plate including the first and the second transistors; forming at least one stressed nitride-based layer, on the first and the second transistors, the layer being voltage stressed; depositing a protective layer so as to cover a first zone of the layer, the first zone covering at least partially the first transistor and leaving a second zone of the layer uncovered, the second zone at least partially covering the second transistor; and modifying a type of stress of the second zone of the layer by implanting hydrogen-based ions from a plasma in the second zone, such that the second zone of the layer is compression stressed.

公开(公告)号：US20160300884A1

公开(公告)日：2016-10-13

申请号：US15094011

申请日：2016-04-08

Applicant: Commissariat a l'energie atomique et aux energies alternatives

Inventor： Laurent GRENOUILLET ,  Yves MORAND ,  Maud VINET

IPC: H01L27/24 ,  H01L29/06 ,  H01L23/31 ,  H01L29/51 ,  H01L29/66 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L23/3107 ,  H01L27/2463 ,  H01L29/0649 ,  H01L29/517 ,  H01L29/66545 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: The invention relates to a process for fabricating an integrated circuit (1), comprising the steps of: providing a substrate (100), the substrate being equipped with first and second dummy gates and with an encapsulation layer (106); removing the first and second dummy gates in order to make first and second grooves (23, 33) in said encapsulation layer (106); simultaneously depositing a gate insulating layer (107) at least in the bottom of the first groove and on a side wall of the second groove; forming a gate electrode of said transistor (2) in the first groove, forming source and drain electrodes of said transistor on either side of said gate electrode, forming first and second electrodes of said memory cell on either side of said gate insulating layer deposited on a side wall of the second groove.

公开(公告)号：US20160254362A1

公开(公告)日：2016-09-01

申请号：US15049468

申请日：2016-02-22

Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives

Inventor： Sylvain MAITREJEAN ,  Emmanuel AUGENDRE ,  Jean-Charles BARBE ,  Benoit MATHIEU ,  Yves MORAND

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/6681 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/31144 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/78696

Abstract: A Method for modifying the strain state of a semiconducting structure, comprising steps to: a) provide at least one first semiconducting structure on a substrate, formed from a semiconducting stack comprising an alternation of elements based on the first semiconducting material and elements based on the second semiconducting material, then b) remove portions of the second semiconducting material from the first structure so as to form empty spaces, c) fill in the empty spaces with a dielectric material, d) form a straining zone on the first structure, based on a first strained material, e) perform appropriate thermal annealing so as to make the dielectric material creep or relax, and cause a change in the strain state of elements based on the first semiconducting material in the structure.

Abstract translation: 一种用于修改半导体结构的应变状态的方法，包括以下步骤：a）在衬底上提供至少一个第一半导体结构，所述第一半导体结构由包括基于所述第一半导体材料的元件交替的半导体堆叠形成，并且基于 第二半导体材料，然后b）从第一结构去除部分第二半导体材料以形成空的空间，c）用介电材料填充空的空间，d）在第一结构上形成应变区，基于 第一应变材料，e）进行适当的热退火，以使电介质材料蠕变或松弛，并引起基于结构中的第一半导体材料的元件的应变状态的变化。

公开(公告)号：US20160133700A1

公开(公告)日：2016-05-12

申请号：US14982852

申请日：2015-12-29

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Sylvain BARRAUD ,  Yves MORAND

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0669 ,  H01L29/413 ,  H01L29/785 ,  H01L29/78648 ,  H01L29/78696 ,  H01L51/057 ,  H01L51/444 ,  H01L2924/13061 ,  H01L2924/13086

Abstract: Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.

Abstract translation: 在半导体绝缘体型衬底上制造微电子器件，该器件设置有给定类型的晶体管，其沟道结构由半导体棒形成，不同于衬底的绝缘层的电介质区域 被提供以替代面向晶体管沟道结构的绝缘层，具体用于该给定类型的晶体管。

公开(公告)号：US20160099326A1

公开(公告)日：2016-04-07

申请号：US14965519

申请日：2015-12-10

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (Crolles 2) SAS

Inventor： Sébastien BARNOLA ,  Yves MORAND ,  Heimanu NIEBOJEWSKI

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/49 ,  H01L29/45 ,  H01L29/06

CPC classification number: H01L29/42372 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/45 ,  H01L29/49 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

Abstract: A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.

公开(公告)号：US20170162672A1

公开(公告)日：2017-06-08

申请号：US15372930

申请日：2016-12-08

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Louis HUTIN ,  Julien BORREL ,  Yves MORAND ,  Fabrice NEMOUCHI

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66643 ,  H01L29/0895 ,  H01L29/66636 ,  H01L29/7839

Abstract: A process for manufacturing a Schottky barrier field-effect transistor is provided. The process includes: providing a structure including a control gate and a semiconductive layer positioned under the gate and having protrusions that protrude laterally with respect to the gate; anisotropically etching at least one of the protrusions by using the control gate as a mask, so as to form a recess in this protrusion, this recess defining a lateral face of the semiconductive layer; depositing a layer of insulator on the lateral face of the semiconductive layer; and depositing a metal in the recess on the layer of insulator so as to form a contact of metal/insulator/semiconductor type between the deposit of metal and the lateral face of the semiconductive layer.